From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yongseok Koh Subject: [PATCH v2] net/mlx5: lift Rx RSS indirection table size limit Date: Tue, 17 Jan 2017 16:39:29 -0800 Message-ID: <20170118003929.35295-1-yskoh@mellanox.com> References: <20170117020644.36481-1-yskoh@mellanox.com> Mime-Version: 1.0 Content-Type: text/plain Cc: , , Yongseok Koh To: Return-path: Received: from EUR03-DB5-obe.outbound.protection.outlook.com (mail-eopbgr40048.outbound.protection.outlook.com [40.107.4.48]) by dpdk.org (Postfix) with ESMTP id 574E6108F for ; Wed, 18 Jan 2017 01:39:44 +0100 (CET) In-Reply-To: <20170117020644.36481-1-yskoh@mellanox.com> List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The size of Rx RSS indirection table was limited by 256, but it is not required anymore for all Mellanox NICs. However, the librte_ether still limits the size by 512. Signed-off-by: Yongseok Koh --- drivers/net/mlx5/mlx5.c | 5 +++-- drivers/net/mlx5/mlx5_defs.h | 3 --- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index 7d40b2445..109d9572d 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -557,8 +557,9 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) priv->ind_table_max_size = exp_device_attr.rx_hash_caps.max_rwq_indirection_table_size; /* Remove this check once DPDK supports larger/variable * indirection tables. */ - if (priv->ind_table_max_size > (unsigned int)RSS_INDIRECTION_TABLE_SIZE) - priv->ind_table_max_size = RSS_INDIRECTION_TABLE_SIZE; + if (priv->ind_table_max_size > + (unsigned int)ETH_RSS_RETA_SIZE_512) + priv->ind_table_max_size = ETH_RSS_RETA_SIZE_512; DEBUG("maximum RX indirection table size is %u", priv->ind_table_max_size); priv->hw_vlan_strip = !!(exp_device_attr.wq_vlan_offloads_cap & diff --git a/drivers/net/mlx5/mlx5_defs.h b/drivers/net/mlx5/mlx5_defs.h index beabb7037..e91d2454a 100644 --- a/drivers/net/mlx5/mlx5_defs.h +++ b/drivers/net/mlx5/mlx5_defs.h @@ -54,9 +54,6 @@ */ #define MLX5_TX_COMP_THRESH 32 -/* RSS Indirection table size. */ -#define RSS_INDIRECTION_TABLE_SIZE 256 - /* * Maximum number of cached Memory Pools (MPs) per TX queue. Each RTE MP * from which buffers are to be transmitted will have to be mapped by this -- 2.11.0