From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Subject: Re: [PATCH v5 00/29] introduce I/O device memory
 read/write operations
Date: Thu, 19 Jan 2017 09:44:54 +0530
Message-ID: <20170119041452.GA18562@localhost.localdomain>
References: <1484637244-7548-1-git-send-email-jerin.jacob@caviumnetworks.com>
 <1484702502-25451-1-git-send-email-jerin.jacob@caviumnetworks.com>
 <3075116.xAOueQvdyS@xps13>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Cc: <dev@dpdk.org>, <konstantin.ananyev@intel.com>,
 <bruce.richardson@intel.com>, <jianbo.liu@linaro.org>,
 <viktorin@rehivetech.com>, <santosh.shukla@caviumnetworks.com>
To: Thomas Monjalon <thomas.monjalon@6wind.com>
Return-path: <dev-bounces@dpdk.org>
Received: from NAM01-BN3-obe.outbound.protection.outlook.com
 (mail-bn3nam01on0058.outbound.protection.outlook.com [104.47.33.58])
 by dpdk.org (Postfix) with ESMTP id 83761FB1A
 for <dev@dpdk.org>; Thu, 19 Jan 2017 05:15:18 +0100 (CET)
Content-Disposition: inline
In-Reply-To: <3075116.xAOueQvdyS@xps13>
List-Id: DPDK patches and discussions <dev.dpdk.org>
List-Unsubscribe: <http://dpdk.org/ml/options/dev>,
 <mailto:dev-request@dpdk.org?subject=unsubscribe>
List-Archive: <http://dpdk.org/ml/archives/dev/>
List-Post: <mailto:dev@dpdk.org>
List-Help: <mailto:dev-request@dpdk.org?subject=help>
List-Subscribe: <http://dpdk.org/ml/listinfo/dev>,
 <mailto:dev-request@dpdk.org?subject=subscribe>
Errors-To: dev-bounces@dpdk.org
Sender: "dev" <dev-bounces@dpdk.org>

On Wed, Jan 18, 2017 at 05:25:22PM +0100, Thomas Monjalon wrote:
> 2017-01-18 06:51, Jerin Jacob:
> > Based on the discussion in the below-mentioned thread,
> > http://dev.dpdk.narkive.com/DpIRqDuy/dpdk-dev-patch-v2-i40e-fix-eth-i40e-dev-init-sequence-on-thunderx
> > 
> > This patchset introduces 8-bit, 16-bit, 32bit, 64bit I/O device
> > memory read/write operations along with the relaxed versions.
> > 
> > The weakly-ordered machine like ARM needs additional I/O barrier for
> > device memory read/write access over PCI bus.
> > By introducing the EAL abstraction for I/O device memory read/write access,
> > The drivers can access I/O device memory in architecture-agnostic manner.
> > 
> > The relaxed version does not have additional I/O memory barrier, useful in
> > accessing the device registers of integrated controllers which
> > implicitly strongly ordered with respect to memory access.
> 
> Applied, thanks

Thanks

> 
> Does it deserve an entry in the release notes?

Not sure. If you like to add this in release note, then I can post a patch for the same.