From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Subject: Re: [PATCH v2 2/2] examples/performance-thread: add
 arm64 support
Date: Thu, 18 May 2017 14:25:45 +0530
Message-ID: <20170518085504.GA13709@jerin>
References: <20170517181949.12002-1-ashwin.sekhar@caviumnetworks.com>
 <20170518073426.14920-1-ashwin.sekhar@caviumnetworks.com>
 <20170518073426.14920-3-ashwin.sekhar@caviumnetworks.com>
Mime-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Cc: john.mcnamara@intel.com, jianbo.liu@linaro.org, dev@dpdk.org,
 halayli@gmail.com
To: Ashwin Sekhar T K <ashwin.sekhar@caviumnetworks.com>
Return-path: <dev-bounces@dpdk.org>
Received: from NAM03-DM3-obe.outbound.protection.outlook.com
 (mail-dm3nam03on0086.outbound.protection.outlook.com [104.47.41.86])
 by dpdk.org (Postfix) with ESMTP id 43F321F5
 for <dev@dpdk.org>; Thu, 18 May 2017 10:56:16 +0200 (CEST)
Content-Disposition: inline
In-Reply-To: <20170518073426.14920-3-ashwin.sekhar@caviumnetworks.com>
List-Id: DPDK patches and discussions <dev.dpdk.org>
List-Unsubscribe: <http://dpdk.org/ml/options/dev>,
 <mailto:dev-request@dpdk.org?subject=unsubscribe>
List-Archive: <http://dpdk.org/ml/archives/dev/>
List-Post: <mailto:dev@dpdk.org>
List-Help: <mailto:dev-request@dpdk.org?subject=help>
List-Subscribe: <http://dpdk.org/ml/listinfo/dev>,
 <mailto:dev-request@dpdk.org?subject=subscribe>
Errors-To: dev-bounces@dpdk.org
Sender: "dev" <dev-bounces@dpdk.org>

-----Original Message-----
> Date: Thu, 18 May 2017 00:34:26 -0700
> From: Ashwin Sekhar T K <ashwin.sekhar@caviumnetworks.com>
> To: jerin.jacob@caviumnetworks.com, john.mcnamara@intel.com,
>  jianbo.liu@linaro.org
> Cc: dev@dpdk.org, Ashwin Sekhar T K <ashwin.sekhar@caviumnetworks.com>
> Subject: [dpdk-dev] [PATCH v2 2/2] examples/performance-thread: add arm64
>  support
> X-Mailer: git-send-email 2.12.2
> 
> Updated Makefile to allow compilation for arm64 architecture.
> 
> Added necessary arm64 support for lthread.
> 
> Fixed minor compilation errors for arm64 compilation.
> 
> Tested the apps l3fwd-thread and lthread_pthread_shim on thunderx
> and x86_64.
> 
> +void
> +ctx_switch(struct ctx *new_ctx __rte_unused, struct ctx *curr_ctx __rte_unused)
> +{
> +	/* SAVE CURRENT CONTEXT */
> +	asm volatile (
> +			/* Save SP */
> +			"mov x3, sp\n"
> +			"str x3, [x1, #0]\n"
> +
> +			/* Save FP and LR */
> +			"stp x29, x30, [x1, #8]\n"
> +
> +			/* Save Callee Saved Regs x19 - x28 */
> +			"stp x19, x20, [x1, #24]\n"
> +			"stp x21, x22, [x1, #40]\n"
> +			"stp x23, x24, [x1, #56]\n"
> +			"stp x25, x26, [x1, #72]\n"
> +			"stp x27, x28, [x1, #88]\n"
> +		     );

IMO, We need to save SIMD registers in the context as well.
x86 code also not doing that, looks like it is an obvious bug in x86 code as
well.