From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jerin Jacob Subject: Re: [PATCH 3/6] eal/arm64: rte pause implementation for arm64 Date: Thu, 18 May 2017 15:46:59 +0530 Message-ID: <20170518101657.GA17993@jerin> References: <20170511101046.26456-1-jerin.jacob@caviumnetworks.com> <20170511101046.26456-3-jerin.jacob@caviumnetworks.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: dev@dpdk.org, thomas@monjalon.net, Jan Viktorin To: Jianbo Liu Return-path: Received: from NAM03-BY2-obe.outbound.protection.outlook.com (mail-by2nam03on0046.outbound.protection.outlook.com [104.47.42.46]) by dpdk.org (Postfix) with ESMTP id B71DC20F for ; Thu, 18 May 2017 12:17:22 +0200 (CEST) Content-Disposition: inline In-Reply-To: List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" -----Original Message----- > Date: Thu, 18 May 2017 17:40:58 +0800 > From: Jianbo Liu > To: Jerin Jacob > Cc: dev@dpdk.org, thomas@monjalon.net, Jan Viktorin > > Subject: Re: [dpdk-dev] [PATCH 3/6] eal/arm64: rte pause implementation for > arm64 > > On 11 May 2017 at 18:10, Jerin Jacob wrote: > > CC: Jianbo Liu > > Signed-off-by: Jerin Jacob > > --- > > lib/librte_eal/common/include/arch/arm/rte_pause.h | 4 ++ > > .../common/include/arch/arm/rte_pause_64.h | 55 ++++++++++++++++++++++ > > 2 files changed, 59 insertions(+) > > create mode 100644 lib/librte_eal/common/include/arch/arm/rte_pause_64.h > > > > diff --git a/lib/librte_eal/common/include/arch/arm/rte_pause.h b/lib/librte_eal/common/include/arch/arm/rte_pause.h > > index 0fe88aba9..9b79405e6 100644 > > --- a/lib/librte_eal/common/include/arch/arm/rte_pause.h > > +++ b/lib/librte_eal/common/include/arch/arm/rte_pause.h > > @@ -37,7 +37,11 @@ > > extern "C" { > > #endif > > > > +#ifdef RTE_ARCH_64 > > +#include > > +#else > > #include > > +#endif > > > > #ifdef __cplusplus > > } > > diff --git a/lib/librte_eal/common/include/arch/arm/rte_pause_64.h b/lib/librte_eal/common/include/arch/arm/rte_pause_64.h > > new file mode 100644 > > index 000000000..cae996de8 > > --- /dev/null > > +++ b/lib/librte_eal/common/include/arch/arm/rte_pause_64.h > > @@ -0,0 +1,55 @@ > > +/* > > + * BSD LICENSE > > + * > > + * Copyright(c) 2017 Cavium. All rights reserved. > > + * > > + * Redistribution and use in source and binary forms, with or without > > + * modification, are permitted provided that the following conditions > > + * are met: > > + * > > + * * Redistributions of source code must retain the above copyright > > + * notice, this list of conditions and the following disclaimer. > > + * * Redistributions in binary form must reproduce the above copyright > > + * notice, this list of conditions and the following disclaimer in > > + * the documentation and/or other materials provided with the > > + * distribution. > > + * * Neither the name of Cavium nor the names of its > > + * contributors may be used to endorse or promote products derived > > + * from this software without specific prior written permission. > > + * > > + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS > > + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT > > + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR > > + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT > > + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, > > + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT > > + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, > > + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY > > + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT > > + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE > > + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > > + */ > > + > > +#ifndef _RTE_PAUSE_ARM64_H_ > > +#define _RTE_PAUSE_ARM64_H_ > > + > > +#ifdef __cplusplus > > +extern "C" { > > +#endif > > + > > +#include > > +#include "generic/rte_pause.h" > > + > > +static inline void rte_pause(void) > > +{ > > + /* YIELD hints the CPU to switch to another thread if possible > > + * and executes as a NOP otherwise. > > I think you can remove the second line if you are trying to explain > what YIELD instruction is. > And I wonder if it can save power as rte_thread is bounded to certain > core and always polling while YIELD is only a hint instruction. AFAIK, It is HW thread not software OS thread.ie Simultaneous Multi-Threading (SMT) or Hyper threading. For example, Cavium 99xx has 4 HW threads per physical core. I agree on comment. I think, I can remove the comment as YIELD is just a hint and varies based on arm64 implementation. Will fix it v2. > > > + */ > > + asm volatile("yield" ::: "memory"); > > +} > > + > > +#ifdef __cplusplus > > +} > > +#endif > > + > > +#endif /* _RTE_PAUSE_ARM64_H_ */ > > -- > > 2.12.2 > >