From mboxrd@z Thu Jan 1 00:00:00 1970 From: Olivier Matz Subject: Re: [PATCH v2] ring: use aligned memzone allocation Date: Thu, 8 Jun 2017 14:45:40 +0200 Message-ID: <20170608144540.5a8e3603@platinum> References: <20170602200337.50743-1-daniel.verkamp@intel.com> <20170602201213.51143-1-daniel.verkamp@intel.com> <2601191342CEEE43887BDE71AB9772583FB05190@IRSMSX109.ger.corp.intel.com> <2601191342CEEE43887BDE71AB9772583FB05216@IRSMSX109.ger.corp.intel.com> <2601191342CEEE43887BDE71AB9772583FB060FD@IRSMSX109.ger.corp.intel.com> <20170606124201.GA43772@bricha3-MOBL3.ger.corp.intel.com> <2601191342CEEE43887BDE71AB9772583FB0644D@IRSMSX109.ger.corp.intel.com> <20170606145628.GB55760@bricha3-MOBL3.ger.corp.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Cc: "Ananyev, Konstantin" , "Verkamp, Daniel" , "dev@dpdk.org" To: Bruce Richardson Return-path: Received: from mail-wm0-f52.google.com (mail-wm0-f52.google.com [74.125.82.52]) by dpdk.org (Postfix) with ESMTP id 0E2A22BA1 for ; Thu, 8 Jun 2017 14:45:43 +0200 (CEST) Received: by mail-wm0-f52.google.com with SMTP id x70so76729232wme.0 for ; Thu, 08 Jun 2017 05:45:43 -0700 (PDT) In-Reply-To: <20170606145628.GB55760@bricha3-MOBL3.ger.corp.intel.com> List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Tue, 6 Jun 2017 15:56:28 +0100, Bruce Richardson wrote: > On Tue, Jun 06, 2017 at 02:19:21PM +0100, Ananyev, Konstantin wrote: > > > > > > > -----Original Message----- > > > From: Richardson, Bruce > > > Sent: Tuesday, June 6, 2017 1:42 PM > > > To: Ananyev, Konstantin > > > Cc: Verkamp, Daniel ; dev@dpdk.org > > > Subject: Re: [dpdk-dev] [PATCH v2] ring: use aligned memzone allocation > > > > > > On Tue, Jun 06, 2017 at 10:59:59AM +0100, Ananyev, Konstantin wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > The PROD/CONS_ALIGN values on x86-64 are set to 2 cache lines, so members > > > > > > of struct rte_ring are 128 byte aligned, > > > > > > >and therefore the whole struct needs 128-byte alignment according to the ABI > > > > > > so that the 128-byte alignment of the fields can be guaranteed. > > > > > > > > > > > > Ah ok, missed the fact that rte_ring is 128B aligned these days. > > > > > > BTW, I probably missed the initial discussion, but what was the reason for that? > > > > > > Konstantin > > > > > > > > > > I don't know why PROD_ALIGN/CONS_ALIGN use 128 byte alignment; it seems unnecessary if the cache line is only 64 bytes. An > > > alternate > > > > > fix would be to just use cache line alignment for these fields (since memzones are already cache line aligned). > > > > > > > > Yes, had the same thought. > > > > > > > > > Maybe there is some deeper reason for the >= 128-byte alignment logic in rte_ring.h? > > > > > > > > Might be, would be good to hear opinion the author of that change. > > > > > > It gives improved performance for core-2-core transfer. > > > > You mean empty cache-line(s) after prod/cons, correct? > > That's ok but why we can't keep them and whole rte_ring aligned on cache-line boundaries? > > Something like that: > > struct rte_ring { > > ... > > struct rte_ring_headtail prod __rte_cache_aligned; > > EMPTY_CACHE_LINE __rte_cache_aligned; > > struct rte_ring_headtail cons __rte_cache_aligned; > > EMPTY_CACHE_LINE __rte_cache_aligned; > > }; > > > > Konstantin > > Sure. That should probably work too. > > /Bruce I also agree with Konstantin's proposal. One question though: since it changes the alignment constraint of the rte_ring structure, I think it is an ABI breakage: a structure including the rte_ring structure inherits from this constraint. How could we handle that, knowing this is probably a rare case?