From mboxrd@z Thu Jan  1 00:00:00 1970
From: Stephen Hemminger <stephen@networkplumber.org>
Subject: Re: [PATCH v2] ring: use aligned memzone allocation
Date: Fri, 9 Jun 2017 10:16:25 -0700
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Cc: "Ananyev, Konstantin" <konstantin.ananyev@intel.com>, "Richardson,
 Bruce" <bruce.richardson@intel.com>, "Verkamp, Daniel"
 <daniel.verkamp@intel.com>, "dev@dpdk.org" <dev@dpdk.org>
To: Yerden Zhumabekov <e_zhumabekov@sts.kz>
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On Fri, 9 Jun 2017 18:47:43 +0600
Yerden Zhumabekov <e_zhumabekov@sts.kz> wrote:

> On 06.06.2017 19:19, Ananyev, Konstantin wrote:
> >  
> >>>> Maybe there is some deeper  reason for the >= 128-byte alignment logic in rte_ring.h?  
> >>> Might be, would be good to hear opinion the author of that change.  
> >> It gives improved performance for core-2-core transfer.  
> > You mean empty cache-line(s) after prod/cons, correct?
> > That's ok but why we can't keep them and whole rte_ring aligned on cache-line boundaries?
> > Something like that:
> > struct rte_ring {
> >     ...
> >     struct rte_ring_headtail prod __rte_cache_aligned;
> >     EMPTY_CACHE_LINE   __rte_cache_aligned;
> >     struct rte_ring_headtail cons __rte_cache_aligned;
> >     EMPTY_CACHE_LINE   __rte_cache_aligned;
> > };
> >
> > Konstantin
> >  
> 
> I'm curious, can anyone explain, how does it actually affect 
> performance? Maybe we can utilize it application code?

I think it is because on Intel CPU's the CPU will speculatively fetch adjacent cache lines.
If these cache lines change, then it will create false sharing.