From mboxrd@z Thu Jan 1 00:00:00 1970 From: Olivier Matz Subject: Re: [PATCH v2] ring: use aligned memzone allocation Date: Fri, 30 Jun 2017 13:36:02 +0200 Message-ID: <20170630133602.63d4f9ca@platinum> References: <20170602200337.50743-1-daniel.verkamp@intel.com> <20170602201213.51143-1-daniel.verkamp@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Cc: dev@dpdk.org To: Daniel Verkamp Return-path: Received: from mail-wm0-f48.google.com (mail-wm0-f48.google.com [74.125.82.48]) by dpdk.org (Postfix) with ESMTP id 1486F5689 for ; Fri, 30 Jun 2017 13:36:05 +0200 (CEST) Received: by mail-wm0-f48.google.com with SMTP id i127so43094407wma.0 for ; Fri, 30 Jun 2017 04:36:05 -0700 (PDT) In-Reply-To: <20170602201213.51143-1-daniel.verkamp@intel.com> List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Fri, 2 Jun 2017 13:12:13 -0700, Daniel Verkamp wrote: > rte_memzone_reserve() provides cache line alignment, but > struct rte_ring may require more than cache line alignment: on x86-64, > it needs 128-byte alignment due to PROD_ALIGN and CONS_ALIGN, which are > 128 bytes, but cache line size is 64 bytes. > > Fixes runtime warnings with UBSan enabled. > > Fixes: d9f0d3a1ffd4 ("ring: remove split cacheline build setting") > > Signed-off-by: Daniel Verkamp Acked-by: Olivier Matz