From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Hemminger Subject: Re: [PATCH v4 2/3] eal: add u64 bit variant for reciprocal Date: Tue, 5 Sep 2017 10:29:01 -0700 Message-ID: <20170905102901.0d9db417@xeon-e3> References: <1504608532-18598-1-git-send-email-pbhagavatula@caviumnetworks.com> <1504608532-18598-2-git-send-email-pbhagavatula@caviumnetworks.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Cc: dev@dpdk.org, cristian.dumitrescu@intel.com To: Pavan Nikhilesh Return-path: Received: from mail-pg0-f44.google.com (mail-pg0-f44.google.com [74.125.83.44]) by dpdk.org (Postfix) with ESMTP id 96397293B for ; Tue, 5 Sep 2017 19:29:10 +0200 (CEST) Received: by mail-pg0-f44.google.com with SMTP id d8so10576451pgt.4 for ; Tue, 05 Sep 2017 10:29:10 -0700 (PDT) In-Reply-To: <1504608532-18598-2-git-send-email-pbhagavatula@caviumnetworks.com> List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Tue, 5 Sep 2017 16:18:51 +0530 Pavan Nikhilesh wrote: > +/** > + * Unsigned 32-bit divisor structure. > + */ > +struct rte_reciprocal_u32 { > uint32_t m; > uint8_t sh1, sh2; > -}; > +} __rte_cache_aligned; > + > +/** > + * Unsigned 64-bit divisor structure. > + */ > +struct rte_reciprocal_u64 { > + uint64_t m; > + uint8_t sh1; > +} __rte_cache_aligned; I understand you want to squeeze every cycle out but it is not required that each of these structures always be cache aligned. They maybe embedded in other structures and having the structure padded so that these elements are cache aligned would take up more space and make cache performance worse. Better off to not put attributes on the structure definitions, and instead let usages of this feature align where appropriate.