From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yongseok Koh Subject: [PATCH v1 5/7] net/mlx5: match Rx completion entry size to cacheline Date: Thu, 5 Oct 2017 16:00:30 -0700 Message-ID: <20171005230032.7548-6-yskoh@mellanox.com> References: <20171005230032.7548-1-yskoh@mellanox.com> Mime-Version: 1.0 Content-Type: text/plain Cc: dev@dpdk.org, Yongseok Koh To: adrien.mazarguil@6wind.com, nelio.laranjeiro@6wind.com Return-path: Received: from EUR01-VE1-obe.outbound.protection.outlook.com (mail-ve1eur01on0059.outbound.protection.outlook.com [104.47.1.59]) by dpdk.org (Postfix) with ESMTP id ED2731B1EC for ; Fri, 6 Oct 2017 01:01:00 +0200 (CEST) In-Reply-To: <20171005230032.7548-1-yskoh@mellanox.com> List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The size of Rx completion entry should match the size of a cacheline. This is already reflected in struct mlx5_cqe by adding 64bytes padding if a cacheline is 128bytes. Some ARM CPUs have 128bytes cacheline. Signed-off-by: Yongseok Koh --- drivers/net/mlx5/mlx5.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index 3362200c8..c23ce11f7 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -1012,6 +1012,9 @@ rte_mlx5_pmd_init(void) setenv("RDMAV_HUGEPAGES_SAFE", "1", 1); /* Don't map UAR to WC if BlueFlame is not used.*/ setenv("MLX5_SHUT_UP_BF", "1", 1); + /* Match the size of Rx completion entry to the size of a cacheline. */ + if (RTE_CACHE_LINE_SIZE == 128) + setenv("MLX5_CQE_SIZE", "128", 0); ibv_fork_init(); rte_pci_register(&mlx5_driver); } -- 2.11.0