From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?iso-8859-1?Q?N=E9lio?= Laranjeiro Subject: Re: [PATCH v1 5/7] net/mlx5: match Rx completion entry size to cacheline Date: Fri, 6 Oct 2017 09:55:10 +0200 Message-ID: <20171006075510.GK15330@autoinstall.dev.6wind.com> References: <20171005230032.7548-1-yskoh@mellanox.com> <20171005230032.7548-6-yskoh@mellanox.com> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Cc: adrien.mazarguil@6wind.com, dev@dpdk.org To: Yongseok Koh Return-path: Received: from mail-wm0-f52.google.com (mail-wm0-f52.google.com [74.125.82.52]) by dpdk.org (Postfix) with ESMTP id 7CF681B269 for ; Fri, 6 Oct 2017 09:55:21 +0200 (CEST) Received: by mail-wm0-f52.google.com with SMTP id m72so1836645wmc.0 for ; Fri, 06 Oct 2017 00:55:21 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20171005230032.7548-6-yskoh@mellanox.com> List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Thu, Oct 05, 2017 at 04:00:30PM -0700, Yongseok Koh wrote: > The size of Rx completion entry should match the size of a cacheline. This > is already reflected in struct mlx5_cqe by adding 64bytes padding if a > cacheline is 128bytes. Some ARM CPUs have 128bytes cacheline. > > Signed-off-by: Yongseok Koh Acked-by: Nelio Laranjeiro -- Nélio Laranjeiro 6WIND