From mboxrd@z Thu Jan 1 00:00:00 1970 From: Adrien Mazarguil Subject: Re: [PATCH v4 8/8] net/mlx4: mitigate Tx path memory barriers Date: Thu, 2 Nov 2017 14:43:24 +0100 Message-ID: <20171102134324.GG24849@6wind.com> References: <1509358049-18854-1-git-send-email-matan@mellanox.com> <1509474093-31388-1-git-send-email-matan@mellanox.com> <1509474093-31388-9-git-send-email-matan@mellanox.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: dev@dpdk.org, Ophir Munk To: Matan Azrad Return-path: Received: from mail-wm0-f68.google.com (mail-wm0-f68.google.com [74.125.82.68]) by dpdk.org (Postfix) with ESMTP id 8D3921B5F1 for ; Thu, 2 Nov 2017 14:43:36 +0100 (CET) Received: by mail-wm0-f68.google.com with SMTP id b9so11555860wmh.0 for ; Thu, 02 Nov 2017 06:43:36 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1509474093-31388-9-git-send-email-matan@mellanox.com> List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Tue, Oct 31, 2017 at 06:21:33PM +0000, Matan Azrad wrote: > Replace most of the memory barriers by IO memory barriers since they > are all targeted to the DRAM; This improves code efficiency for > systems which force store order between different addresses. > > Only the doorbell register store should be protected by memory barrier > since it is targeted to the PCI memory domain. > > Limit pre byte count store IO memory barrier for systems with cache > line size smaller than 64B (TXBB size). > > This patch improves Tx performance by 0.2MPPS for one segment 64B > packets via 1 queue with 1 core test. > > Signed-off-by: Matan Azrad Acked-by: Adrien Mazarguil -- Adrien Mazarguil 6WIND