From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Hemminger Subject: Re: [PATCH] bus/pci: forbid VA as IOVA mode if IOMMU address width too small Date: Mon, 8 Jan 2018 07:38:41 -0800 Message-ID: <20180108073841.43c15072@xeon-e3> References: <20180108135127.25869-1-maxime.coquelin@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Cc: dev@dpdk.org, stable@dpdk.org, jianfeng.tan@intel.com, santosh.shukla@caviumnetworks.com, anatoly.burakov@intel.com, thomas@monjalon.net, peterx@redhat.com To: Maxime Coquelin Return-path: Received: from mail-pf0-f193.google.com (mail-pf0-f193.google.com [209.85.192.193]) by dpdk.org (Postfix) with ESMTP id BDAF11B1C5 for ; Mon, 8 Jan 2018 16:38:51 +0100 (CET) Received: by mail-pf0-f193.google.com with SMTP id e76so1401440pfk.1 for ; Mon, 08 Jan 2018 07:38:51 -0800 (PST) In-Reply-To: <20180108135127.25869-1-maxime.coquelin@redhat.com> List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Mon, 8 Jan 2018 14:51:27 +0100 Maxime Coquelin wrote: > +static inline bool > +pci_one_device_iommu_support_va(struct rte_pci_device *dev) > +{ > +#if defined(RTE_ARCH_PPC_64) > + return false; > +#elif defined(RTE_ARCH_X86) > + The cleaner way to handle this kind of ifdef is: #ifdef RTE_ARCH_X86 static bool pci_one_device_iommu_support_va(struct rte_pci_device *dev) { .... } #elif defined(RTE_ARCH_PPC_64) static inline bool pci_one_device_iommu_support_va(struct rte_pci_device *dev) { return false; } #endif What about AMD64? Do all ARM processors have IOMMU, I think not.