From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jianbo Liu Subject: Re: [PATCH v2 1/8] eal: introduce DMA memory barriers Date: Tue, 16 Jan 2018 17:10:41 +0800 Message-ID: <20180116091040.GA15629@arm.com> References: <20171227042824.33373-1-yskoh@mellanox.com> <20180116011050.18866-1-yskoh@mellanox.com> <20180116011050.18866-2-yskoh@mellanox.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Cc: Yongseok Koh , adrien.mazarguil@6wind.com, nelio.laranjeiro@6wind.com, jerin.jacob@caviumnetworks.com, dev@dpdk.org To: Andrew Rybchenko Return-path: Received: from EUR01-DB5-obe.outbound.protection.outlook.com (mail-db5eur01on0049.outbound.protection.outlook.com [104.47.2.49]) by dpdk.org (Postfix) with ESMTP id BE2F512009 for ; Tue, 16 Jan 2018 10:12:06 +0100 (CET) Content-Disposition: inline In-Reply-To: List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The 01/16/2018 10:49, Andrew Rybchenko wrote: > On 01/16/2018 04:10 AM, Yongseok Koh wrote: > >This commit introduces rte_dma_wmb() and rte_dma_rmb(), in order to > >guarantee the ordering of coherent shared memory between the CPU and a D= MA > >capable device. > > > >Signed-off-by: Yongseok Koh > >--- > > lib/librte_eal/common/include/generic/rte_atomic.h | 18 ++++++++++++++= ++++ > > 1 file changed, 18 insertions(+) > > > >diff --git a/lib/librte_eal/common/include/generic/rte_atomic.h b/lib/li= brte_eal/common/include/generic/rte_atomic.h > >index 16af5ca57..2e0503ce6 100644 > >--- a/lib/librte_eal/common/include/generic/rte_atomic.h > >+++ b/lib/librte_eal/common/include/generic/rte_atomic.h > >@@ -98,6 +98,24 @@ static inline void rte_io_wmb(void); > > */ > > static inline void rte_io_rmb(void); > >+/** > >+ * Write memory barrier for coherent memory between lcore and IO device > >+ * > >+ * Guarantees that the STORE operations on coherent memory that > >+ * precede the rte_dma_wmb() call are visible to I/O device before the > >+ * STORE operations that follow it. > >+ */ > >+static inline void rte_dma_wmb(void); > >+ > >+/** > >+ * Read memory barrier for coherent memory between lcore and IO device > >+ * > >+ * Guarantees that the LOAD operations on coherent memory updated by > >+ * IO device that precede the rte_dma_rmb() call are visible to CPU > >+ * before the LOAD operations that follow it. > >+ */ > >+static inline void rte_dma_rmb(void); > >+ > > #endif /* __DOXYGEN__ */ > > /** > > I'm not an ARMv8 expert so, my comments could be a bit ignorant. > I'd like to understand the difference between io and added here dma > barriers. > The difference should be clearly explained. Otherwise we'll constantly hi= t > on incorrect choice of barrier type. > Also I don't understand why "dma" name is chosen taking into account > that definition is bound to coherent memory between lcore and IO device. A good explanation can be found here. https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?= id=3D1077fa36f23e259858caf6f269a47393a5aff523 -- IMPORTANT NOTICE: The contents of this email and any attachments are confid= ential and may also be privileged. If you are not the intended recipient, p= lease notify the sender immediately and do not disclose the contents to any= other person, use it for any purpose, or store or copy the information in = any medium. Thank you.