From mboxrd@z Thu Jan 1 00:00:00 1970 From: Adrien Mazarguil Subject: Re: [PATCH] ethdev: increase flow type limit from 32 to 64 Date: Tue, 16 Jan 2018 12:13:26 +0100 Message-ID: <20180116111326.GD4256@6wind.com> References: <1511785787-127452-1-git-send-email-kirill.rybalchenko@intel.com> <20171204174304.GK4062@6wind.com> <696B43C21188DF4F9C9091AAE4789B824E2B6786@IRSMSX108.ger.corp.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: "dev@dpdk.org" , "Wu, Jingjing" , "Xing, Beilei" , "johndale@cisco.com" , "neescoba@cisco.com" , "nelio.laranjeiro@6wind.com" , "yskoh@mellanox.com" , "Lu, Wenzhuo" , "Ananyev, Konstantin" , "Chilikin, Andrey" To: "Rybalchenko, Kirill" Return-path: Received: from mail-wm0-f41.google.com (mail-wm0-f41.google.com [74.125.82.41]) by dpdk.org (Postfix) with ESMTP id 04D41A495 for ; Tue, 16 Jan 2018 12:13:39 +0100 (CET) Received: by mail-wm0-f41.google.com with SMTP id 143so7501830wma.5 for ; Tue, 16 Jan 2018 03:13:38 -0800 (PST) Content-Disposition: inline In-Reply-To: <696B43C21188DF4F9C9091AAE4789B824E2B6786@IRSMSX108.ger.corp.intel.com> List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Tue, Jan 09, 2018 at 03:16:13PM +0000, Rybalchenko, Kirill wrote: > > -----Original Message----- > > From: Adrien Mazarguil [mailto:adrien.mazarguil@6wind.com] > > Sent: Monday 4 December 2017 17:43 > > To: Rybalchenko, Kirill > > Cc: dev@dpdk.org; Wu, Jingjing ; Xing, Beilei > > ; johndale@cisco.com; neescoba@cisco.com; > > nelio.laranjeiro@6wind.com; yskoh@mellanox.com; Lu, Wenzhuo > > ; Ananyev, Konstantin > > ; Chilikin, Andrey > > > > Subject: Re: [PATCH] ethdev: increase flow type limit from 32 to 64 > > > > Hi Kirill, > > > > On Mon, Nov 27, 2017 at 12:29:47PM +0000, Kirill Rybalchenko wrote: > > > Increase the internal limit for flow types from 32 to 64 to support > > > future flow type extensions. > > > Change type of variables from uint32_t[] to uint64_t[]: > > > rte_eth_fdir_info.flow_types_mask > > > rte_eth_hash_global_conf.sym_hash_enable_mask > > > rte_eth_hash_global_conf.valid_bit_mask > > > > > > This modification affects the following components: > > > net/i40e > > > net/enic > > > net/mlx5 > > > net/ixgbe > > > app/testpmd > > > > > > Signed-off-by: Kirill Rybalchenko > > > > Can you elaborate a bit on the need for these changes? > > Have you considered implementing those future extensions through > > rte_flow instead? > > Hi Adrien, this is not a new feature but rather fix of existing limitation. > In current implementation the symmetric hash mask and flow mask are > represented by 32-bit variable, while hardware bitmask has 64 bits. > Unfortunately, this modification changes ABI of the library as it changes size > of rte_eth_fdir_info structure. All related PMDs (listed above) had to be modified > accordingly. OK, no problem with this change. I assume you'll re-submit it since you sent a deprecation notice, we'll review/ack subsequent mlx5 patches. -- Adrien Mazarguil 6WIND