From mboxrd@z Thu Jan 1 00:00:00 1970 From: Shweta Choudaha Subject: [PATCH v2] net/ixgbe: Add API to update SBP bit Date: Tue, 10 Apr 2018 16:42:46 +0100 Message-ID: <20180410154246.102440-1-shweta.choudaha@gmail.com> References: <20180223115913.19266-2-shweta.choudaha@gmail.com> Cc: wenzhuo.lu@intel.com, konstantin.ananyev@intel.com, helin.zhang@intel.com, ferruh.yigit@intel.com, shweta.choudaha@att.com To: dev@dpdk.org Return-path: Received: from mail-wm0-f67.google.com (mail-wm0-f67.google.com [74.125.82.67]) by dpdk.org (Postfix) with ESMTP id 805081B86A for ; Tue, 10 Apr 2018 17:42:51 +0200 (CEST) Received: by mail-wm0-f67.google.com with SMTP id x4so24187755wmh.5 for ; Tue, 10 Apr 2018 08:42:51 -0700 (PDT) In-Reply-To: <20180223115913.19266-2-shweta.choudaha@gmail.com> List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shweta Choudaha Add ixgbe API to enable SBP bit in FCTRL register to allow receiving packets that may otherwise be considered length errors by ixgbe and dropped Signed-off-by: Shweta Choudaha Reviewed-by: Chas Williams Reviewed-by: Luca Boccassi --- drivers/net/ixgbe/rte_pmd_ixgbe.c | 28 ++++++++++++++++++++++++++++ drivers/net/ixgbe/rte_pmd_ixgbe.h | 13 +++++++++++++ drivers/net/ixgbe/rte_pmd_ixgbe_version.map | 6 ++++++ 3 files changed, 47 insertions(+) diff --git a/drivers/net/ixgbe/rte_pmd_ixgbe.c b/drivers/net/ixgbe/rte_pmd_ixgbe.c index d8ca8ca31..3b6f68f9e 100644 --- a/drivers/net/ixgbe/rte_pmd_ixgbe.c +++ b/drivers/net/ixgbe/rte_pmd_ixgbe.c @@ -880,6 +880,34 @@ rte_pmd_ixgbe_set_tc_bw_alloc(uint16_t port, return 0; } +int __rte_experimental +rte_pmd_ixgbe_upd_fctrl_sbp(uint16_t port, int enable) +{ + struct ixgbe_hw *hw; + struct rte_eth_dev *dev; + uint32_t fctrl; + + RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); + dev = &rte_eth_devices[port]; + if (!is_ixgbe_supported(dev)) + return -ENOTSUP; + + hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + if (!hw) + return -ENOTSUP; + + fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); + + /* If 'enable' set the SBP bit else clear it */ + if (enable) + fctrl |= IXGBE_FCTRL_SBP; + else + fctrl &= ~(IXGBE_FCTRL_SBP); + + IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); + return 0; +} + #ifdef RTE_LIBRTE_IXGBE_BYPASS int rte_pmd_ixgbe_bypass_init(uint16_t port_id) diff --git a/drivers/net/ixgbe/rte_pmd_ixgbe.h b/drivers/net/ixgbe/rte_pmd_ixgbe.h index 11a9f334b..a3026bd98 100644 --- a/drivers/net/ixgbe/rte_pmd_ixgbe.h +++ b/drivers/net/ixgbe/rte_pmd_ixgbe.h @@ -637,4 +637,17 @@ enum { ((x) > RTE_PMD_IXGBE_BYPASS_TMT_OFF && \ (x) < RTE_PMD_IXGBE_BYPASS_TMT_NUM)) +/** + * @param port + * The port identifier of the Ethernet device. + * @param enable + * 0 to disable and nonzero to enable 'SBP' bit in FCTRL register + * to receive all packets + * @return + * - (0) if successful. + * - (-ENODEV) if *port* invalid. + * - (-ENOTSUP) if hardware doesn't support this feature. + */ +int __rte_experimental +rte_pmd_ixgbe_upd_fctrl_sbp(uint16_t port, int enable); #endif /* _PMD_IXGBE_H_ */ diff --git a/drivers/net/ixgbe/rte_pmd_ixgbe_version.map b/drivers/net/ixgbe/rte_pmd_ixgbe_version.map index bf776742c..ff6bd0336 100644 --- a/drivers/net/ixgbe/rte_pmd_ixgbe_version.map +++ b/drivers/net/ixgbe/rte_pmd_ixgbe_version.map @@ -52,3 +52,9 @@ DPDK_17.08 { rte_pmd_ixgbe_bypass_wd_timeout_show; rte_pmd_ixgbe_bypass_wd_timeout_store; } DPDK_17.05; + +EXPERIMENTAL { + global: + + rte_pmd_ixgbe_upd_fctrl_sbp; +} DPDK_18.05; -- 2.11.0