From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jerin Jacob Kollanukkaran Subject: Re: [EXT] [PATCH v8 3/3] spinlock: reimplement with atomic one-way barrier builtins Date: Thu, 14 Mar 2019 14:22:31 +0000 Message-ID: <20190314142224.GA10102@dc5-eodlnx05.marvell.com> References: <20181220104246.5590-1-gavin.hu@arm.com> <1552031797-146710-4-git-send-email-gavin.hu@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Cc: "dev@dpdk.org" , "nd@arm.com" , "thomas@monjalon.net" , "hemant.agrawal@nxp.com" , "nipun.gupta@nxp.com" , "Honnappa.Nagarahalli@arm.com" , "i.maximets@samsung.com" , "chaozhu@linux.vnet.ibm.com" , "stable@dpdk.org" To: Gavin Hu Return-path: In-Reply-To: <1552031797-146710-4-git-send-email-gavin.hu@arm.com> Content-Language: en-US Content-ID: <47E783601067A04F9A297D288CCE4A1F@namprd18.prod.outlook.com> List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Fri, Mar 08, 2019 at 03:56:37PM +0800, Gavin Hu wrote: > External Email >=20 > ---------------------------------------------------------------------- > The __sync builtin based implementation generates full memory barriers > ('dmb ish') on Arm platforms. Using C11 atomic builtins to generate one w= ay > barriers. >=20 > Here is the assembly code of __sync_compare_and_swap builtin. > __sync_bool_compare_and_swap(dst, exp, src); > 0x000000000090f1b0 <+16>: e0 07 40 f9 ldr x0, [sp, #8] > 0x000000000090f1b4 <+20>: e1 0f 40 79 ldrh w1, [sp, #6] > 0x000000000090f1b8 <+24>: e2 0b 40 79 ldrh w2, [sp, #4] > 0x000000000090f1bc <+28>: 21 3c 00 12 and w1, w1, #0xffff > 0x000000000090f1c0 <+32>: 03 7c 5f 48 ldxrh w3, [x0] > 0x000000000090f1c4 <+36>: 7f 00 01 6b cmp w3, w1 > 0x000000000090f1c8 <+40>: 61 00 00 54 b.ne 0x90f1d4 > // b.any > 0x000000000090f1cc <+44>: 02 fc 04 48 stlxrh w4, w2, [x0] > 0x000000000090f1d0 <+48>: 84 ff ff 35 cbnz w4, 0x90f1c0 > > 0x000000000090f1d4 <+52>: bf 3b 03 d5 dmb ish > 0x000000000090f1d8 <+56>: e0 17 9f 1a cset w0, eq // eq =3D non= e >=20 > The benchmarking results showed constant improvements on all available > platforms: > 1. Cavium ThunderX2: 126% performance; > 2. Hisilicon 1616: 30%; > 3. Qualcomm Falkor: 13%; > 4. Marvell ARMADA 8040 with A72 cores on macchiatobin: 3.7% >=20 > Here is the example test result on TX2: > $sudo ./build/app/test -l 16-27 -- i > RTE>>spinlock_autotest >=20 > *** spinlock_autotest without this patch *** > Test with lock on 12 cores... > Core [16] Cost Time =3D 53886 us > Core [17] Cost Time =3D 53605 us > Core [18] Cost Time =3D 53163 us > Core [19] Cost Time =3D 49419 us > Core [20] Cost Time =3D 34317 us > Core [21] Cost Time =3D 53408 us > Core [22] Cost Time =3D 53970 us > Core [23] Cost Time =3D 53930 us > Core [24] Cost Time =3D 53283 us > Core [25] Cost Time =3D 51504 us > Core [26] Cost Time =3D 50718 us > Core [27] Cost Time =3D 51730 us > Total Cost Time =3D 612933 us >=20 > *** spinlock_autotest with this patch *** > Test with lock on 12 cores... > Core [16] Cost Time =3D 18808 us > Core [17] Cost Time =3D 29497 us > Core [18] Cost Time =3D 29132 us > Core [19] Cost Time =3D 26150 us > Core [20] Cost Time =3D 21892 us > Core [21] Cost Time =3D 24377 us > Core [22] Cost Time =3D 27211 us > Core [23] Cost Time =3D 11070 us > Core [24] Cost Time =3D 29802 us > Core [25] Cost Time =3D 15793 us > Core [26] Cost Time =3D 7474 us > Core [27] Cost Time =3D 29550 us > Total Cost Time =3D 270756 us >=20 > In the tests on ThunderX2, with more cores contending, the performance ga= in > was even higher, indicating the __atomic implementation scales up better > than __sync. >=20 > Fixes: af75078fece3 ("first public release") > Cc: stable@dpdk.org >=20 > Signed-off-by: Gavin Hu > Reviewed-by: Phil Yang > Reviewed-by: Honnappa Nagarahalli > Reviewed-by: Ola Liljedahl > Reviewed-by: Steve Capper Reviewed-by: Jerin Jacob