* [PATCH 1/5] bus/dpaa: add FQ shutdown and improve logging
2025-10-07 5:00 [PATCH 0/5] DPAA specific changes Gagandeep Singh
@ 2025-10-07 5:00 ` Gagandeep Singh
2025-10-07 5:00 ` [PATCH 2/5] net/dpaa: Support IEEE1588 by timesync API Gagandeep Singh
` (4 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Gagandeep Singh @ 2025-10-07 5:00 UTC (permalink / raw)
To: dev, Hemant Agrawal, Sachin Saxena
adding a FQ shutdown functionality to ensure proper cleanup of
frame queues during queue setup. This helps reset the
queues reliably and prevents potential resource leaks or
stale state issues.
Additionally, update logging to use DPAA_BUS_ERR instead
of pr_err for better consistency and clarity in error
reporting within the DPAA bus subsystem.
These changes enhance maintainability and improve
debugging experience.
Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
---
drivers/bus/dpaa/base/qbman/qman.c | 394 +++++++++++++++++++++++++---
drivers/bus/dpaa/include/fsl_qman.h | 3 +
drivers/net/dpaa/dpaa_ethdev.c | 3 +
3 files changed, 369 insertions(+), 31 deletions(-)
diff --git a/drivers/bus/dpaa/base/qbman/qman.c b/drivers/bus/dpaa/base/qbman/qman.c
index 60087c55a1..6ce3690366 100644
--- a/drivers/bus/dpaa/base/qbman/qman.c
+++ b/drivers/bus/dpaa/base/qbman/qman.c
@@ -10,7 +10,8 @@
#include <bus_dpaa_driver.h>
#include <rte_eventdev.h>
#include <rte_byteorder.h>
-
+#include <rte_dpaa_logs.h>
+#include <eal_export.h>
#include <dpaa_bits.h>
/* Compilation constants */
@@ -137,7 +138,7 @@ static inline int table_push_fq(struct qman_portal *p, struct qman_fq *fq)
int ret = fqtree_push(&p->retire_table, fq);
if (ret)
- pr_err("ERROR: double FQ-retirement %d\n", fq->fqid);
+ DPAA_BUS_ERR("ERROR: double FQ-retirement %d", fq->fqid);
return ret;
}
@@ -161,7 +162,7 @@ int qman_setup_fq_lookup_table(size_t num_entries)
/* Allocate 1 more entry since the first entry is not used */
qman_fq_lookup_table = vmalloc((num_entries * sizeof(void *)));
if (!qman_fq_lookup_table) {
- pr_err("QMan: Could not allocate fq lookup table\n");
+ DPAA_BUS_ERR("QMan: Could not allocate fq lookup table");
return -ENOMEM;
}
memset(qman_fq_lookup_table, 0, num_entries * sizeof(void *));
@@ -349,7 +350,8 @@ static int drain_mr_fqrni(struct qm_portal *p)
}
if ((msg->ern.verb & QM_MR_VERB_TYPE_MASK) != QM_MR_VERB_FQRNI) {
/* We aren't draining anything but FQRNIs */
- pr_err("Found verb 0x%x in MR\n", msg->ern.verb);
+ DPAA_BUS_ERR("Found verb 0x%x and after mask = 0x%x in MR",
+ msg->ern.verb, msg->ern.verb & QM_MR_VERB_TYPE_MASK);
return -1;
}
qm_mr_next(p);
@@ -423,11 +425,11 @@ static inline void qm_eqcr_finish(struct qm_portal *portal)
DPAA_ASSERT(!eqcr->busy);
#endif
if (pi != EQCR_PTR2IDX(eqcr->cursor))
- pr_crit("losing uncommitted EQCR entries\n");
+ DPAA_BUS_ERR("losing uncommitted EQCR entries");
if (ci != eqcr->ci)
- pr_crit("missing existing EQCR completions\n");
+ DPAA_BUS_ERR("missing existing EQCR completions");
if (eqcr->ci != EQCR_PTR2IDX(eqcr->cursor))
- pr_crit("EQCR destroyed unquiesced\n");
+ DPAA_BUS_ERR("EQCR destroyed unquiesced");
}
static inline int qm_dqrr_init(struct qm_portal *portal,
@@ -515,6 +517,7 @@ qman_init_portal(struct qman_portal *portal,
int ret;
u32 isdr;
+
p = &portal->p;
if (!c)
@@ -540,30 +543,68 @@ qman_init_portal(struct qman_portal *portal,
*/
if (qm_eqcr_init(p, qm_eqcr_pvb,
portal->use_eqcr_ci_stashing, 1)) {
- pr_err("Qman EQCR initialisation failed\n");
+ DPAA_BUS_ERR("Qman EQCR initialisation failed");
+ goto fail_eqcr;
+ }
+ if (qm_dqrr_init(p, c, qm_dqrr_dpush, qm_dqrr_pvb,
+ qm_dqrr_cdc, DQRR_MAXFILL)) {
+ DPAA_BUS_ERR("Qman DQRR initialisation failed");
+ goto fail_dqrr;
+ }
+ if (qm_mr_init(p, qm_mr_pvb, qm_mr_cci)) {
+ DPAA_BUS_ERR("Qman MR initialisation failed");
+ goto fail_mr;
+ }
+ if (qm_mc_init(p)) {
+ DPAA_BUS_ERR("Qman MC initialisation failed");
+ goto fail_mc;
+ }
+
+ /* Reset portal before use */
+ DPAA_BUS_DEBUG("Reset portal = %p", p);
+ qm_dqrr_sdqcr_set(p, 0);
+ qm_eqcr_cce_update(p);
+ qm_eqcr_cce_update(p);
+ qm_mc_finish(p);
+ qm_mr_finish(p);
+ qm_dqrr_finish(p);
+ qm_eqcr_finish(p);
+
+ p->addr.ce = c->addr_virt[DPAA_PORTAL_CE];
+ p->addr.ci = c->addr_virt[DPAA_PORTAL_CI];
+ /*
+ * If CI-stashing is used, the current defaults use a threshold of 3,
+ * and stash with high-than-DQRR priority.
+ */
+ if (qm_eqcr_init(p, qm_eqcr_pvb,
+ portal->use_eqcr_ci_stashing, 1)) {
+ DPAA_BUS_ERR("Qman EQCR initialisation failed");
goto fail_eqcr;
}
if (qm_dqrr_init(p, c, qm_dqrr_dpush, qm_dqrr_pvb,
qm_dqrr_cdc, DQRR_MAXFILL)) {
- pr_err("Qman DQRR initialisation failed\n");
+ DPAA_BUS_ERR("Qman DQRR initialisation failed");
goto fail_dqrr;
}
if (qm_mr_init(p, qm_mr_pvb, qm_mr_cci)) {
- pr_err("Qman MR initialisation failed\n");
+ DPAA_BUS_ERR("Qman MR initialisation failed");
goto fail_mr;
}
if (qm_mc_init(p)) {
- pr_err("Qman MC initialisation failed\n");
+ DPAA_BUS_ERR("Qman MC initialisation failed");
goto fail_mc;
}
+
/* static interrupt-gating controls */
qm_dqrr_set_ithresh(p, 0);
qm_mr_set_ithresh(p, 0);
qm_isr_set_iperiod(p, 0);
portal->cgrs = kmalloc(2 * sizeof(*cgrs), GFP_KERNEL);
- if (!portal->cgrs)
+ if (!portal->cgrs) {
+ DPAA_BUS_ERR("CGRS allocation fails");
goto fail_cgrs;
+ }
/* initial snapshot is no-depletion */
qman_cgrs_init(&portal->cgrs[1]);
if (cgrs)
@@ -580,6 +621,7 @@ qman_init_portal(struct qman_portal *portal,
portal->dqrr_disable_ref = 0;
portal->cb_dc_ern = NULL;
sprintf(buf, "qportal-%d", c->channel);
+ DPAA_BUS_DEBUG("PORTAL ID = %d and %p", c->channel, p);
dpa_rbtree_init(&portal->retire_table);
isdr = 0xffffffff;
qm_isr_disable_write(p, isdr);
@@ -589,7 +631,7 @@ qman_init_portal(struct qman_portal *portal,
snprintf(portal->irqname, MAX_IRQNAME, IRQNAME, c->cpu);
if (request_irq(c->irq, portal_isr, 0, portal->irqname,
portal)) {
- pr_err("request_irq() failed\n");
+ DPAA_BUS_ERR("request_irq() failed");
goto fail_irq;
}
@@ -598,19 +640,22 @@ qman_init_portal(struct qman_portal *portal,
qm_isr_disable_write(p, isdr);
ret = qm_eqcr_get_fill(p);
if (ret) {
- pr_err("Qman EQCR unclean\n");
+ DPAA_BUS_ERR("Qman EQCR unclean");
goto fail_eqcr_empty;
}
isdr &= ~(QM_PIRQ_DQRI | QM_PIRQ_MRI);
qm_isr_disable_write(p, isdr);
if (qm_dqrr_current(p)) {
- pr_err("Qman DQRR unclean\n");
+ DPAA_BUS_ERR("Qman DQRR unclean");
qm_dqrr_cdc_consume_n(p, 0xffff);
}
if (qm_mr_current(p) && drain_mr_fqrni(p)) {
/* special handling, drain just in case it's a few FQRNIs */
- if (drain_mr_fqrni(p))
+ DPAA_BUS_ERR("Draining MR FQRNI");
+ if (drain_mr_fqrni(p)) {
+ DPAA_BUS_ERR("Draining MR FQRNI fails");
goto fail_dqrr_mr_empty;
+ }
}
/* Success */
portal->config = c;
@@ -652,7 +697,7 @@ qman_alloc_global_portal(struct qm_portal_config *q_pcfg)
return &global_portals[i];
}
}
- pr_err("No portal available (%x)\n", MAX_GLOBAL_PORTALS);
+ DPAA_BUS_ERR("No portal available (%x)", MAX_GLOBAL_PORTALS);
return NULL;
}
@@ -702,6 +747,7 @@ void qman_destroy_portal(struct qman_portal *qm)
{
const struct qm_portal_config *pcfg;
+ DPAA_BUS_DEBUG("In destroy portal = %p", &qm->p);
/* Stop dequeues on the portal */
qm_dqrr_sdqcr_set(&qm->p, 0);
@@ -1488,7 +1534,7 @@ int qman_create_fq(u32 fqid, u32 flags, struct qman_fq *fq)
cpu_relax();
DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCC_VERB_QUERYFQ);
if (mcr->result != QM_MCR_RESULT_OK) {
- pr_err("QUERYFQ failed: %s\n", mcr_result_str(mcr->result));
+ DPAA_BUS_ERR("QUERYFQ failed: %s", mcr_result_str(mcr->result));
goto err;
}
fqd = mcr->queryfq.fqd;
@@ -1500,7 +1546,7 @@ int qman_create_fq(u32 fqid, u32 flags, struct qman_fq *fq)
cpu_relax();
DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCC_VERB_QUERYFQ_NP);
if (mcr->result != QM_MCR_RESULT_OK) {
- pr_err("QUERYFQ_NP failed: %s\n", mcr_result_str(mcr->result));
+ DPAA_BUS_ERR("QUERYFQ_NP failed: %s", mcr_result_str(mcr->result));
goto err;
}
np = mcr->queryfq_np;
@@ -2026,7 +2072,7 @@ int qman_query_wq(u8 query_dedicated, struct qm_mcr_querywq *wq)
wq->wq_len[i] = be32_to_cpu(mcr->querywq.wq_len[i]);
}
if (res != QM_MCR_RESULT_OK) {
- pr_err("QUERYWQ failed: %s\n", mcr_result_str(res));
+ DPAA_BUS_ERR("QUERYWQ failed: %s", mcr_result_str(res));
return -EIO;
}
return 0;
@@ -2053,7 +2099,7 @@ int qman_testwrite_cgr(struct qman_cgr *cgr, u64 i_bcnt,
if (res == QM_MCR_RESULT_OK)
*result = mcr->cgrtestwrite;
if (res != QM_MCR_RESULT_OK) {
- pr_err("CGR TEST WRITE failed: %s\n", mcr_result_str(res));
+ DPAA_BUS_ERR("CGR TEST WRITE failed: %s", mcr_result_str(res));
return -EIO;
}
return 0;
@@ -2077,7 +2123,7 @@ int qman_query_cgr(struct qman_cgr *cgr, struct qm_mcr_querycgr *cgrd)
if (res == QM_MCR_RESULT_OK)
*cgrd = mcr->querycgr;
if (res != QM_MCR_RESULT_OK) {
- pr_err("QUERY_CGR failed: %s\n", mcr_result_str(res));
+ DPAA_BUS_ERR("QUERY_CGR failed: %s", mcr_result_str(res));
return -EIO;
}
cgrd->cgr.wr_parm_g.word =
@@ -2111,7 +2157,7 @@ int qman_query_congestion(struct qm_mcr_querycongestion *congestion)
if (res == QM_MCR_RESULT_OK)
*congestion = mcr->querycongestion;
if (res != QM_MCR_RESULT_OK) {
- pr_err("QUERY_CONGESTION failed: %s\n", mcr_result_str(res));
+ DPAA_BUS_ERR("QUERY_CONGESTION failed: %s", mcr_result_str(res));
return -EIO;
}
for (i = 0; i < ARRAY_SIZE(congestion->state.state); i++)
@@ -2660,6 +2706,287 @@ int qman_delete_cgr(struct qman_cgr *cgr)
return ret;
}
+#define GENMASK(h, l) \
+ (((~0U) >> (sizeof(unsigned int) * 8 - ((h) - (l) + 1))) << (l))
+
+/* 'fqid' is a 24-bit field in every h/w descriptor */
+#define QM_FQID_MASK GENMASK(23, 0)
+#define qm_fqid_set(p, v) ((p)->fqid = cpu_to_be32((v) & QM_FQID_MASK))
+#define qm_fqid_get(p) (be32_to_cpu((p)->fqid) & QM_FQID_MASK)
+
+static int
+_qm_mr_consume_and_match_verb(struct qm_portal *p, int v)
+{
+ const struct qm_mr_entry *msg;
+ int found = 0;
+
+ qm_mr_pvb_update(p);
+ msg = qm_mr_current(p);
+ while (msg) {
+ if ((msg->ern.verb & QM_MR_VERB_TYPE_MASK) == v)
+ found = 1;
+ qm_mr_next(p);
+ qm_mr_cci_consume_to_current(p);
+ qm_mr_pvb_update(p);
+ msg = qm_mr_current(p);
+ }
+ return found;
+}
+
+static int
+_qm_dqrr_consume_and_match(struct qm_portal *p, u32 fqid, int s,
+ bool wait)
+{
+ const struct qm_dqrr_entry *dqrr;
+ int found = 0;
+
+ do {
+ qm_dqrr_pvb_update(p);
+ dqrr = qm_dqrr_current(p);
+ if (!dqrr)
+ cpu_relax();
+ } while (wait && !dqrr);
+
+ while (dqrr) {
+ if (qm_fqid_get(dqrr) == fqid && (dqrr->stat & s))
+ found = 1;
+
+ qm_dqrr_cdc_consume_1ptr(p, dqrr, 0);
+ qm_dqrr_pvb_update(p);
+ qm_dqrr_next(p);
+ dqrr = qm_dqrr_current(p);
+ }
+ return found;
+}
+
+#define QM_MCR_TIMEOUT 10000 /* us */
+
+static inline int
+qm_mc_result_timeout(struct qm_portal *portal,
+ struct qm_mc_result **mcr)
+{
+ int timeout = QM_MCR_TIMEOUT;
+
+ do {
+ *mcr = qm_mc_result(portal);
+ if (*mcr)
+ break;
+ usleep(1);
+ } while (--timeout);
+
+ return timeout;
+}
+
+#define qm_mr_drain(p, V) \
+ _qm_mr_consume_and_match_verb(p, QM_MR_VERB_##V)
+
+#define qm_dqrr_drain(p, f, S) \
+ _qm_dqrr_consume_and_match(p, f, QM_DQRR_STAT_##S, false)
+
+#define qm_dqrr_drain_wait(p, f, S) \
+ _qm_dqrr_consume_and_match(p, f, QM_DQRR_STAT_##S, true)
+
+#define qm_dqrr_drain_nomatch(p) \
+ _qm_dqrr_consume_and_match(p, 0, 0, false)
+
+RTE_EXPORT_INTERNAL_SYMBOL(qman_shutdown_fq_new)
+int
+qman_shutdown_fq_new(u32 fqid)
+{
+ struct qman_portal *p;
+ struct qm_mc_command *mcc;
+ struct qm_mc_result *mcr;
+ int orl_empty, drain = 0, ret = 0;
+ u32 res;
+ u8 state;
+ u32 channel, wq;
+ u16 dest_wq;
+
+ DPAA_BUS_DEBUG("In shutdown for queue = %x", fqid);
+ p = get_affine_portal();
+ /* Determine the state of the FQID */
+ mcc = qm_mc_start(&p->p);
+ mcc->queryfq_np.fqid = cpu_to_be32(fqid);
+ qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ_NP);
+ if (!qm_mc_result_timeout(&p->p, &mcr)) {
+ DPAA_BUS_ERR("QUERYFQ_NP timeout");
+ ret = -ETIMEDOUT;
+ goto out;
+ }
+ state = mcr->queryfq_np.state & QM_MCR_NP_STATE_MASK;
+ if (state == QM_MCR_NP_STATE_OOS) {
+ DPAA_BUS_ERR("Already in OOS");
+ goto out; /* Already OOS, no need to do anymore checks */
+ }
+
+ /* Query which channel the FQ is using */
+ mcc = qm_mc_start(&p->p);
+ mcc->queryfq.fqid = cpu_to_be32(fqid);
+ qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ);
+ if (!qm_mc_result_timeout(&p->p, &mcr)) {
+ DPAA_BUS_ERR("QUERYFQ timeout");
+ ret = -ETIMEDOUT;
+ goto out;
+ }
+
+ /* Need to store these since the MCR gets reused */
+ dest_wq = be16_to_cpu(mcr->queryfq.fqd.dest_wq);
+ channel = dest_wq & 0x7;
+ wq = dest_wq >> 3;
+
+ switch (state) {
+ case QM_MCR_NP_STATE_TEN_SCHED:
+ case QM_MCR_NP_STATE_TRU_SCHED:
+ case QM_MCR_NP_STATE_ACTIVE:
+ case QM_MCR_NP_STATE_PARKED:
+ DPAA_BUS_DEBUG("In shutdown state is %d", state);
+ orl_empty = 0;
+ mcc = qm_mc_start(&p->p);
+ mcc->alterfq.fqid = cpu_to_be32(fqid);
+ qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_RETIRE);
+ if (!qm_mc_result_timeout(&p->p, &mcr)) {
+ DPAA_BUS_ERR("ALTER_RETIRE timeout");
+ ret = -ETIMEDOUT;
+ goto out;
+ }
+ res = mcr->result; /* Make a copy as we reuse MCR below */
+
+ if (res == QM_MCR_RESULT_OK)
+ drain_mr_fqrni(&p->p);
+
+ if (res == QM_MCR_RESULT_PENDING) {
+ /*
+ * Need to wait for the FQRN in the message ring, which
+ * will only occur once the FQ has been drained. In
+ * order for the FQ to drain the portal needs to be set
+ * to dequeue from the channel the FQ is scheduled on
+ */
+ int found_fqrn = 0;
+
+ /* Flag that we need to drain FQ */
+ drain = 1;
+
+ __maybe_unused u16 dequeue_wq = 0;
+ if (channel >= qm_channel_pool1 &&
+ channel < (u16)(qm_channel_pool1 + 15)) {
+ /* Pool channel, enable the bit in the portal */
+ dequeue_wq = (channel -
+ qm_channel_pool1 + 1) << 4 | wq;
+ } else if (channel < qm_channel_pool1) {
+ /* Dedicated channel */
+ dequeue_wq = wq;
+ } else {
+ DPAA_BUS_ERR("Can't recover FQ 0x%x, ch: 0x%x",
+ fqid, channel);
+ ret = -EBUSY;
+ goto out;
+ }
+ /* Set the sdqcr to drain this channel */
+ if (channel < qm_channel_pool1)
+ qm_dqrr_sdqcr_set(&p->p,
+ QM_SDQCR_TYPE_ACTIVE |
+ QM_SDQCR_CHANNELS_DEDICATED);
+ else
+ qm_dqrr_sdqcr_set(&p->p,
+ QM_SDQCR_TYPE_ACTIVE |
+ QM_SDQCR_CHANNELS_POOL_CONV
+ (channel));
+ do {
+ /* Keep draining DQRR while checking the MR*/
+ qm_dqrr_drain_nomatch(&p->p);
+ /* Process message ring too */
+ found_fqrn = qm_mr_drain(&p->p,
+ FQRN);
+ cpu_relax();
+ } while (!found_fqrn);
+ /* Restore SDQCR */
+ qm_dqrr_sdqcr_set(&p->p,
+ p->sdqcr);
+ }
+ if (res != QM_MCR_RESULT_OK &&
+ res != QM_MCR_RESULT_PENDING) {
+ DPAA_BUS_ERR("retire_fq failed: FQ 0x%x, res=0x%x",
+ fqid, res);
+ ret = -EIO;
+ goto out;
+ }
+ if (!(mcr->alterfq.fqs & QM_MCR_FQS_ORLPRESENT)) {
+ /*
+ * ORL had no entries, no need to wait until the
+ * ERNs come in
+ */
+ orl_empty = 1;
+ }
+ /*
+ * Retirement succeeded, check to see if FQ needs
+ * to be drained
+ */
+ if (drain || mcr->alterfq.fqs & QM_MCR_FQS_NOTEMPTY) {
+ /* FQ is Not Empty, drain using volatile DQ commands */
+ do {
+ u32 vdqcr = fqid | QM_VDQCR_NUMFRAMES_SET(3);
+
+ qm_dqrr_vdqcr_set(&p->p, vdqcr);
+ /*
+ * Wait for a dequeue and process the dequeues,
+ * making sure to empty the ring completely
+ */
+ } while (!qm_dqrr_drain_wait(&p->p, fqid, FQ_EMPTY));
+ }
+ while (!orl_empty) {
+ /* Wait for the ORL to have been completely drained */
+ orl_empty = qm_mr_drain(&p->p, FQRL);
+ cpu_relax();
+ }
+ mcc = qm_mc_start(&p->p);
+ mcc->alterfq.fqid = cpu_to_be32(fqid);
+ qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_OOS);
+ if (!qm_mc_result_timeout(&p->p, &mcr)) {
+ DPAA_BUS_ERR("OOS Timeout");
+ ret = -ETIMEDOUT;
+ goto out;
+ }
+
+ if (mcr->result != QM_MCR_RESULT_OK) {
+ DPAA_BUS_ERR("OOS after drain fail: FQ 0x%x (0x%x)",
+ fqid, mcr->result);
+ ret = -EIO;
+ goto out;
+ }
+ break;
+
+ case QM_MCR_NP_STATE_RETIRED:
+ /* Send OOS Command */
+ mcc = qm_mc_start(&p->p);
+ mcc->alterfq.fqid = cpu_to_be32(fqid);
+ qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_OOS);
+ if (!qm_mc_result_timeout(&p->p, &mcr)) {
+ DPAA_BUS_ERR("In RTEIRED to OOS timeout");
+ ret = -ETIMEDOUT;
+ goto out;
+ }
+
+ if (mcr->result != QM_MCR_RESULT_OK) {
+ DPAA_BUS_ERR("OOS fail: FQ 0x%x (0x%x)",
+ fqid, mcr->result);
+ ret = -EIO;
+ goto out;
+ }
+ break;
+
+ case QM_MCR_NP_STATE_OOS:
+ /* Done */
+ break;
+
+ default:
+ ret = -EIO;
+ }
+
+out:
+ return ret;
+}
+
+RTE_EXPORT_INTERNAL_SYMBOL(qman_shutdown_fq)
int qman_shutdown_fq(u32 fqid)
{
struct qman_portal *p;
@@ -2683,8 +3010,10 @@ int qman_shutdown_fq(u32 fqid)
cpu_relax();
DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ_NP);
state = mcr->queryfq_np.state & QM_MCR_NP_STATE_MASK;
- if (state == QM_MCR_NP_STATE_OOS)
+ if (state == QM_MCR_NP_STATE_OOS) {
+ DPAA_BUS_ERR("Already in OOS state");
return 0; /* Already OOS, no need to do anymore checks */
+ }
/* Query which channel the FQ is using */
mcc = qm_mc_start(low_p);
@@ -2714,6 +3043,9 @@ int qman_shutdown_fq(u32 fqid)
QM_MCR_VERB_ALTER_RETIRE);
result = mcr->result; /* Make a copy as we reuse MCR below */
+ if (result == QM_MCR_RESULT_OK)
+ drain_mr_fqrni(low_p);
+
if (result == QM_MCR_RESULT_PENDING) {
/* Need to wait for the FQRN in the message ring, which
* will only occur once the FQ has been drained. In
@@ -2737,7 +3069,7 @@ int qman_shutdown_fq(u32 fqid)
/* Dedicated channel */
dequeue_wq = wq;
} else {
- pr_info("Cannot recover FQ 0x%x,"
+ DPAA_BUS_ERR("Cannot recover FQ 0x%x,"
" it is scheduled on channel 0x%x",
fqid, channel);
return -EBUSY;
@@ -2782,8 +3114,8 @@ int qman_shutdown_fq(u32 fqid)
if (result != QM_MCR_RESULT_OK &&
result != QM_MCR_RESULT_PENDING) {
/* error */
- pr_err("qman_retire_fq failed on FQ 0x%x,"
- " result=0x%x\n", fqid, result);
+ DPAA_BUS_ERR("qman_retire_fq failed on FQ 0x%x, result=0x%x",
+ fqid, result);
return -1;
}
if (!(mcr->alterfq.fqs & QM_MCR_FQS_ORLPRESENT)) {
@@ -2853,8 +3185,8 @@ int qman_shutdown_fq(u32 fqid)
DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) ==
QM_MCR_VERB_ALTER_OOS);
if (mcr->result != QM_MCR_RESULT_OK) {
- pr_err(
- "OOS after drain Failed on FQID 0x%x, result 0x%x\n",
+ DPAA_BUS_ERR(
+ "OOS after drain Failed on FQID 0x%x, result 0x%x",
fqid, mcr->result);
return -1;
}
@@ -2869,8 +3201,8 @@ int qman_shutdown_fq(u32 fqid)
cpu_relax();
DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) ==
QM_MCR_VERB_ALTER_OOS);
- if (mcr->result) {
- pr_err("OOS Failed on FQID 0x%x\n", fqid);
+ if (mcr->result != QM_MCR_RESULT_OK) {
+ DPAA_BUS_ERR("OOS Failed on FQID 0x%x", fqid);
return -1;
}
return 0;
diff --git a/drivers/bus/dpaa/include/fsl_qman.h b/drivers/bus/dpaa/include/fsl_qman.h
index 71d5b16878..5b6015a876 100644
--- a/drivers/bus/dpaa/include/fsl_qman.h
+++ b/drivers/bus/dpaa/include/fsl_qman.h
@@ -1894,7 +1894,10 @@ static inline void qman_release_fqid(u32 fqid)
void qman_seed_fqid_range(u32 fqid, unsigned int count);
+__rte_internal
int qman_shutdown_fq(u32 fqid);
+__rte_internal
+int qman_shutdown_fq_new(u32 fqid);
/**
* qman_reserve_fqid_range - Reserve the specified range of frame queue IDs
diff --git a/drivers/net/dpaa/dpaa_ethdev.c b/drivers/net/dpaa/dpaa_ethdev.c
index 34b691fde7..30a0c97a8b 100644
--- a/drivers/net/dpaa/dpaa_ethdev.c
+++ b/drivers/net/dpaa/dpaa_ethdev.c
@@ -1134,6 +1134,9 @@ int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)",
queue_idx, rxq->fqid);
+ /* Shutdown FQ before configure */
+ qman_shutdown_fq(rxq->fqid);
+
if (!fif->num_profiles) {
if (dpaa_intf->bp_info && dpaa_intf->bp_info->bp &&
dpaa_intf->bp_info->mp != mp) {
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 2/5] net/dpaa: Support IEEE1588 by timesync API
2025-10-07 5:00 [PATCH 0/5] DPAA specific changes Gagandeep Singh
2025-10-07 5:00 ` [PATCH 1/5] bus/dpaa: add FQ shutdown and improve logging Gagandeep Singh
@ 2025-10-07 5:00 ` Gagandeep Singh
2025-10-07 5:00 ` [PATCH 3/5] bus/dpaa: Disable qman Invalid Enqueue State interrupt Gagandeep Singh
` (3 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Gagandeep Singh @ 2025-10-07 5:00 UTC (permalink / raw)
To: dev, Hemant Agrawal, Sachin Saxena; +Cc: Jun Yang
From: Jun Yang <jun.yang@nxp.com>
Enable IEEE1588 by timesync API instead of devargs.
DPAA1 HW parser has no capability to identify ptp packets
from ingress traffic, remove ptp identification code from
driver RX callback which impacts performance significantly.
Signed-off-by: Jun Yang <jun.yang@nxp.com>
---
doc/guides/nics/dpaa.rst | 3 -
drivers/bus/dpaa/base/qbman/qman.c | 18 +++---
drivers/bus/dpaa/include/fsl_qman.h | 5 +-
drivers/common/dpaax/dpaax_ptp.h | 95 +++++++++++++++++++++++++++++
drivers/net/dpaa/dpaa_ethdev.c | 15 ++---
drivers/net/dpaa/dpaa_ethdev.h | 13 ++--
drivers/net/dpaa/dpaa_ptp.c | 50 ++++++++++++---
drivers/net/dpaa/dpaa_rxtx.c | 93 +++++++++++++---------------
drivers/net/dpaa/dpaa_rxtx.h | 2 +-
9 files changed, 204 insertions(+), 90 deletions(-)
create mode 100644 drivers/common/dpaax/dpaax_ptp.h
diff --git a/doc/guides/nics/dpaa.rst b/doc/guides/nics/dpaa.rst
index 8cd57b21f3..8ffe31ce32 100644
--- a/doc/guides/nics/dpaa.rst
+++ b/doc/guides/nics/dpaa.rst
@@ -275,9 +275,6 @@ for details.
Done
testpmd>
-* Use dev arg option ``drv_ieee1588=1`` to enable IEEE 1588 support
- at driver level, e.g. ``dpaa:fm1-mac3,drv_ieee1588=1``.
-
* Use dev arg option ``recv_err_pkts=1`` to receive all packets including error packets
and thus disabling hardware based packet handling at driver level,
e.g. ``dpaa:fm1-mac3,recv_err_pkts=1``.
diff --git a/drivers/bus/dpaa/base/qbman/qman.c b/drivers/bus/dpaa/base/qbman/qman.c
index 6ce3690366..ec1fdb7cd3 100644
--- a/drivers/bus/dpaa/base/qbman/qman.c
+++ b/drivers/bus/dpaa/base/qbman/qman.c
@@ -1234,14 +1234,14 @@ u16 qman_affine_channel(int cpu)
return affine_channels[cpu];
}
-unsigned int qman_portal_poll_rx(unsigned int poll_limit,
- void **bufs,
- struct qman_portal *p)
+uint32_t
+qman_portal_poll_rx(uint32_t poll_limit, void **bufs,
+ struct qman_portal *p, struct qman_fq_cb *cb)
{
struct qm_portal *portal = &p->p;
register struct qm_dqrr *dqrr = &portal->dqrr;
struct qm_dqrr_entry *dq[QM_DQRR_SIZE], *shadow[QM_DQRR_SIZE];
- struct qman_fq *fq;
+ struct qman_fq *fq[QM_DQRR_SIZE];
unsigned int limit = 0, rx_number = 0;
uint32_t consume = 0;
@@ -1275,12 +1275,12 @@ unsigned int qman_portal_poll_rx(unsigned int poll_limit,
/* SDQCR: context_b points to the FQ */
#ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
- fq = qman_fq_lookup_table[dq[rx_number]->contextB];
+ fq[rx_number] = qman_fq_lookup_table[dq[rx_number]->contextB];
#else
- fq = (void *)dq[rx_number]->contextB;
+ fq[rx_number] = (void *)dq[rx_number]->contextB;
#endif
- if (fq->cb.dqrr_prepare)
- fq->cb.dqrr_prepare(shadow[rx_number],
+ if (fq[rx_number]->cb.dqrr_prepare)
+ fq[rx_number]->cb.dqrr_prepare(shadow[rx_number],
&bufs[rx_number]);
consume |= (1 << (31 - DQRR_PTR2IDX(shadow[rx_number])));
@@ -1289,7 +1289,7 @@ unsigned int qman_portal_poll_rx(unsigned int poll_limit,
} while (++limit < poll_limit);
if (rx_number)
- fq->cb.dqrr_dpdk_pull_cb(&fq, shadow, bufs, rx_number);
+ cb->dqrr_dpdk_pull_cb(fq, shadow, bufs, rx_number);
/* Consume all the DQRR enries together */
qm_out(DQRR_DCAP, (1 << 8) | consume);
diff --git a/drivers/bus/dpaa/include/fsl_qman.h b/drivers/bus/dpaa/include/fsl_qman.h
index 5b6015a876..93611cc234 100644
--- a/drivers/bus/dpaa/include/fsl_qman.h
+++ b/drivers/bus/dpaa/include/fsl_qman.h
@@ -1393,8 +1393,9 @@ int qman_fq_portal_irqsource_remove(struct qman_portal *p, u32 bits);
u16 qman_affine_channel(int cpu);
__rte_internal
-unsigned int qman_portal_poll_rx(unsigned int poll_limit,
- void **bufs, struct qman_portal *q);
+uint32_t
+qman_portal_poll_rx(uint32_t poll_limit, void **bufs,
+ struct qman_portal *p, struct qman_fq_cb *cb);
/**
* qman_set_vdq - Issue a volatile dequeue command
diff --git a/drivers/common/dpaax/dpaax_ptp.h b/drivers/common/dpaax/dpaax_ptp.h
new file mode 100644
index 0000000000..b73c16c986
--- /dev/null
+++ b/drivers/common/dpaax/dpaax_ptp.h
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright 2025 NXP
+ */
+
+#ifndef _DPAAX_PTP_H_
+#define _DPAAX_PTP_H_
+#include <stdlib.h>
+#include <rte_ether.h>
+#include <rte_ip.h>
+#include <rte_udp.h>
+
+#define UDP_PTP_EVENT_DST_PORT 319
+#define UDP_PTP_GENERAL_DST_PORT 320
+
+struct __rte_packed_begin rte_dpaax_ptp_header {
+ uint8_t tsmt; /* transportSpecific | messageType */
+ uint8_t ver; /* reserved | versionPTP */
+ rte_be16_t msg_len;
+ uint8_t domain_number;
+ uint8_t rsv;
+ uint8_t flags[2];
+ rte_be64_t correction;
+ uint8_t unused[];
+} __rte_packed_end;
+
+static inline struct rte_dpaax_ptp_header *
+dpaax_timesync_ptp_parse_header(struct rte_mbuf *buf,
+ uint16_t *ts_offset, int *is_udp)
+{
+ struct rte_ether_hdr *eth = rte_pktmbuf_mtod(buf, void *);
+ void *next_hdr;
+ rte_be16_t ether_type;
+ struct rte_vlan_hdr *vlan;
+ struct rte_ipv4_hdr *ipv4;
+ struct rte_ipv6_hdr *ipv6;
+ struct rte_udp_hdr *udp;
+ struct rte_dpaax_ptp_header *ptp = NULL;
+ uint16_t offset = offsetof(struct rte_dpaax_ptp_header, correction);
+
+ if (is_udp)
+ *is_udp = false;
+
+ offset += sizeof(struct rte_ether_hdr);
+ if (eth->ether_type == htons(RTE_ETHER_TYPE_1588)) {
+ ptp = (void *)(eth + 1);
+ goto quit;
+ }
+
+ if (eth->ether_type == htons(RTE_ETHER_TYPE_VLAN)) {
+ vlan = (void *)(eth + 1);
+ ether_type = vlan->eth_proto;
+ next_hdr = (void *)(vlan + 1);
+ offset += sizeof(struct rte_vlan_hdr);
+ if (ether_type == htons(RTE_ETHER_TYPE_1588)) {
+ ptp = next_hdr;
+ goto quit;
+ }
+ } else {
+ ether_type = eth->ether_type;
+ next_hdr = (void *)(eth + 1);
+ }
+
+ if (ether_type == htons(RTE_ETHER_TYPE_IPV4)) {
+ ipv4 = next_hdr;
+ offset += sizeof(struct rte_ipv4_hdr);
+ if (ipv4->next_proto_id != IPPROTO_UDP)
+ return NULL;
+ udp = (void *)(ipv4 + 1);
+ goto parse_udp;
+ } else if (ether_type == htons(RTE_ETHER_TYPE_IPV6)) {
+ ipv6 = next_hdr;
+ offset += sizeof(struct rte_ipv6_hdr);
+ if (ipv6->proto != IPPROTO_UDP)
+ return NULL;
+ udp = (void *)(ipv6 + 1);
+ goto parse_udp;
+ } else {
+ return NULL;
+ }
+parse_udp:
+ offset += sizeof(struct rte_udp_hdr);
+ if (udp->dst_port != UDP_PTP_EVENT_DST_PORT &&
+ udp->dst_port != UDP_PTP_GENERAL_DST_PORT)
+ return NULL;
+ ptp = (void *)(udp + 1);
+ if (is_udp)
+ *is_udp = true;
+quit:
+ if (ts_offset)
+ *ts_offset = offset;
+
+ return ptp;
+}
+
+#endif /* _DPAAX_PTP_H_ */
diff --git a/drivers/net/dpaa/dpaa_ethdev.c b/drivers/net/dpaa/dpaa_ethdev.c
index 30a0c97a8b..43aab98339 100644
--- a/drivers/net/dpaa/dpaa_ethdev.c
+++ b/drivers/net/dpaa/dpaa_ethdev.c
@@ -52,7 +52,6 @@
#include <process.h>
#include <fmlib/fm_ext.h>
-#define DRIVER_IEEE1588 "drv_ieee1588"
#define CHECK_INTERVAL 100 /* 100ms */
#define MAX_REPEAT_TIME 90 /* 9s (90 * 100ms) in total */
#define DRIVER_RECV_ERR_PKTS "recv_err_pkts"
@@ -88,7 +87,6 @@ static uint64_t dev_tx_offloads_nodis =
static int is_global_init;
static int fmc_q = 1; /* Indicates the use of static fmc for distribution */
static int default_q; /* use default queue - FMC is not executed*/
-int dpaa_ieee_1588; /* use to indicate if IEEE 1588 is enabled for the driver */
bool dpaa_enable_recv_err_pkts; /* Enable main queue to receive error packets */
/* At present we only allow up to 4 push mode queues as default - as each of
@@ -1998,6 +1996,7 @@ static int dpaa_tx_queue_init(struct qman_fq *fq,
}
};
int ret;
+ struct dpaa_if *dpaa_intf = fq->dpaa_intf;
ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
QMAN_FQ_FLAG_TO_DCPORTAL, fq);
@@ -2011,7 +2010,7 @@ static int dpaa_tx_queue_init(struct qman_fq *fq,
opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY;
opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE;
opts.fqd.context_b = 0;
- if (dpaa_ieee_1588) {
+ if (dpaa_intf->ts_enable) {
opts.fqd.context_a.lo = 0;
opts.fqd.context_a.hi =
fman_intf->fman->dealloc_bufs_mask_hi;
@@ -2063,7 +2062,7 @@ static int dpaa_tx_queue_init(struct qman_fq *fq,
return ret;
}
-static int
+int
dpaa_tx_conf_queue_init(struct qman_fq *fq)
{
struct qm_mcc_initfq opts = {0};
@@ -2261,9 +2260,6 @@ dpaa_dev_init(struct rte_eth_dev *eth_dev)
dpaa_intf->ifid = dev_id;
dpaa_intf->cfg = cfg;
- if (dpaa_get_devargs(dev->devargs, DRIVER_IEEE1588))
- dpaa_ieee_1588 = 1;
-
if (dpaa_get_devargs(dev->devargs, DRIVER_RECV_ERR_PKTS))
dpaa_enable_recv_err_pkts = 1;
@@ -2432,14 +2428,14 @@ dpaa_dev_init(struct rte_eth_dev *eth_dev)
if (dpaa_intf->cgr_tx)
dpaa_intf->cgr_tx[loop].cgrid = cgrid_tx[loop];
+ dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop],
fman_intf,
dpaa_intf->cgr_tx ? &dpaa_intf->cgr_tx[loop] : NULL);
if (ret)
goto free_tx;
- dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
- if (dpaa_ieee_1588) {
+ if (dpaa_intf->ts_enable) {
ret = dpaa_tx_conf_queue_init(&dpaa_intf->tx_conf_queues[loop]);
if (ret)
goto free_tx;
@@ -2731,6 +2727,5 @@ static struct rte_dpaa_driver rte_dpaa_pmd = {
RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd);
RTE_PMD_REGISTER_PARAM_STRING(net_dpaa,
- DRIVER_IEEE1588 "=<int>"
DRIVER_RECV_ERR_PKTS "=<int>");
RTE_LOG_REGISTER_DEFAULT(dpaa_logtype_pmd, NOTICE);
diff --git a/drivers/net/dpaa/dpaa_ethdev.h b/drivers/net/dpaa/dpaa_ethdev.h
index be9398004f..f400030a5c 100644
--- a/drivers/net/dpaa/dpaa_ethdev.h
+++ b/drivers/net/dpaa/dpaa_ethdev.h
@@ -119,7 +119,6 @@ enum {
#define FMC_FILE "/tmp/fmc.bin"
extern struct rte_mempool *dpaa_tx_sg_pool;
-extern int dpaa_ieee_1588;
/* PMD related logs */
extern int dpaa_logtype_pmd;
@@ -154,10 +153,12 @@ struct dpaa_if {
void *netenv_handle;
void *scheme_handle[2];
uint32_t scheme_count;
+ int ts_enable;
/*stores timestamp of last received packet on dev*/
uint64_t rx_timestamp;
/*stores timestamp of last received tx confirmation packet on dev*/
uint64_t tx_timestamp;
+ uint64_t tx_old_timestamp;
/* stores pointer to next tx_conf queue that should be processed,
* it corresponds to last packet transmitted
*/
@@ -244,6 +245,9 @@ struct dpaa_if_rx_bmi_stats {
uint32_t fmbm_rbdc; /**< Rx Buffers Deallocate Counter*/
};
+int
+dpaa_tx_conf_queue_init(struct qman_fq *fq);
+
int
dpaa_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
struct timespec *timestamp);
@@ -256,18 +260,17 @@ dpaa_timesync_disable(struct rte_eth_dev *dev);
int
dpaa_timesync_read_time(struct rte_eth_dev *dev,
- struct timespec *timestamp);
+ struct timespec *timestamp);
int
dpaa_timesync_write_time(struct rte_eth_dev *dev,
- const struct timespec *timestamp);
+ const struct timespec *timestamp);
int
dpaa_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
int
dpaa_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
- struct timespec *timestamp,
- uint32_t flags __rte_unused);
+ struct timespec *timestamp, uint32_t flags __rte_unused);
uint8_t
fm_default_vsp_id(struct fman_if *fif);
diff --git a/drivers/net/dpaa/dpaa_ptp.c b/drivers/net/dpaa/dpaa_ptp.c
index 8482666745..e9b332c571 100644
--- a/drivers/net/dpaa/dpaa_ptp.c
+++ b/drivers/net/dpaa/dpaa_ptp.c
@@ -17,20 +17,40 @@
#include <dpaa_rxtx.h>
int
-dpaa_timesync_enable(struct rte_eth_dev *dev __rte_unused)
+dpaa_timesync_enable(struct rte_eth_dev *dev)
{
+ struct dpaa_if *dpaa_intf = dev->data->dev_private;
+ int loop, ret = 0;
+
+ for (loop = 0; loop < MAX_DPAA_CORES; loop++) {
+ if (!dpaa_intf->tx_queues[loop].tx_conf_queue) {
+ ret = dpaa_tx_conf_queue_init(&dpaa_intf->tx_conf_queues[loop]);
+ if (ret)
+ break;
+ dpaa_intf->tx_conf_queues[loop].dpaa_intf = dpaa_intf;
+ dpaa_intf->tx_queues[loop].tx_conf_queue = &dpaa_intf->tx_conf_queues[loop];
+ }
+ }
+
+ if (ret)
+ return ret;
+
+ dpaa_intf->ts_enable = true;
return 0;
}
int
-dpaa_timesync_disable(struct rte_eth_dev *dev __rte_unused)
+dpaa_timesync_disable(struct rte_eth_dev *dev)
{
+ struct dpaa_if *dpaa_intf = dev->data->dev_private;
+
+ dpaa_intf->ts_enable = false;
return 0;
}
int
dpaa_timesync_read_time(struct rte_eth_dev *dev,
- struct timespec *timestamp)
+ struct timespec *timestamp)
{
uint32_t *tmr_cnt_h, *tmr_cnt_l;
struct fman_if *fif;
@@ -50,7 +70,7 @@ dpaa_timesync_read_time(struct rte_eth_dev *dev,
int
dpaa_timesync_write_time(struct rte_eth_dev *dev,
- const struct timespec *ts)
+ const struct timespec *ts)
{
uint32_t *tmr_cnt_h, *tmr_cnt_l;
struct fman_if *fif;
@@ -88,15 +108,21 @@ dpaa_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
int
dpaa_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
- struct timespec *timestamp)
+ struct timespec *timestamp)
{
struct dpaa_if *dpaa_intf = dev->data->dev_private;
+ int read_count = 10000;
- if (dpaa_intf->next_tx_conf_queue) {
- while (!dpaa_intf->tx_timestamp)
+ if (dpaa_intf->ts_enable && dpaa_intf->next_tx_conf_queue) {
+ while (dpaa_intf->tx_timestamp == dpaa_intf->tx_old_timestamp) {
dpaa_eth_tx_conf(dpaa_intf->next_tx_conf_queue);
+ if (read_count <= 0)
+ return -EAGAIN;
+ read_count--;
+ }
+ dpaa_intf->tx_old_timestamp = dpaa_intf->tx_timestamp;
} else {
- return -1;
+ return -ENOTSUP;
}
*timestamp = rte_ns_to_timespec(dpaa_intf->tx_timestamp);
@@ -105,10 +131,14 @@ dpaa_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
int
dpaa_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
- struct timespec *timestamp,
- uint32_t flags __rte_unused)
+ struct timespec *timestamp, uint32_t flags __rte_unused)
{
struct dpaa_if *dpaa_intf = dev->data->dev_private;
+
+ if (!dpaa_intf->ts_enable)
+ return -ENOTSUP;
+
*timestamp = rte_ns_to_timespec(dpaa_intf->rx_timestamp);
+
return 0;
}
diff --git a/drivers/net/dpaa/dpaa_rxtx.c b/drivers/net/dpaa/dpaa_rxtx.c
index 4dca63ea7e..c5e393159a 100644
--- a/drivers/net/dpaa/dpaa_rxtx.c
+++ b/drivers/net/dpaa/dpaa_rxtx.c
@@ -45,6 +45,7 @@
#include <fsl_qman.h>
#include <fsl_bman.h>
#include <dpaa_of.h>
+#include <dpaax_ptp.h>
#include <netcfg.h>
#ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
@@ -234,12 +235,11 @@ dpaa_slow_parsing(struct rte_mbuf *m,
m->packet_type |= RTE_PTYPE_L4_SCTP;
}
-static inline void dpaa_eth_packet_info(struct rte_mbuf *m, void *fd_virt_addr)
+static inline void
+dpaa_eth_packet_info(struct dpaa_if *dpaa_intf, struct rte_mbuf *m,
+ struct annotations_t *annot)
{
- struct annotations_t *annot = GET_ANNOTATIONS(fd_virt_addr);
uint64_t prs = *((uintptr_t *)(&annot->parse)) & DPAA_PARSE_MASK;
- struct rte_ether_hdr *eth_hdr =
- rte_pktmbuf_mtod(m, struct rte_ether_hdr *);
DPAA_DP_LOG(DEBUG, " Parsing mbuf: %p with annotations: %p", m, annot);
@@ -360,9 +360,11 @@ static inline void dpaa_eth_packet_info(struct rte_mbuf *m, void *fd_virt_addr)
m->ol_flags |= RTE_MBUF_F_RX_VLAN;
/* Packet received without stripping the vlan */
- if (eth_hdr->ether_type == htons(RTE_ETHER_TYPE_1588)) {
- m->ol_flags |= RTE_MBUF_F_RX_IEEE1588_PTP;
- m->ol_flags |= RTE_MBUF_F_RX_IEEE1588_TMST;
+ if (unlikely(dpaa_intf->ts_enable)) {
+ if (dpaax_timesync_ptp_parse_header(m, NULL, NULL)) {
+ m->ol_flags |= RTE_MBUF_F_RX_IEEE1588_PTP;
+ m->ol_flags |= RTE_MBUF_F_RX_IEEE1588_TMST;
+ }
}
}
@@ -468,7 +470,7 @@ dpaa_unsegmented_checksum(struct rte_mbuf *mbuf, struct qm_fd *fd_arr)
}
static struct rte_mbuf *
-dpaa_eth_sg_to_mbuf(const struct qm_fd *fd, uint32_t ifid)
+dpaa_eth_sg_to_mbuf(struct dpaa_if *dpaa_intf, const struct qm_fd *fd)
{
struct dpaa_bp_info *bp_info = DPAA_BPID_TO_POOL_INFO(fd->bpid);
struct rte_mbuf *first_seg, *prev_seg, *cur_seg, *temp;
@@ -499,7 +501,7 @@ dpaa_eth_sg_to_mbuf(const struct qm_fd *fd, uint32_t ifid)
(void **)&first_seg, 1, 1);
#endif
- first_seg->port = ifid;
+ first_seg->port = dpaa_intf->ifid;
first_seg->nb_segs = 1;
first_seg->ol_flags = 0;
prev_seg = first_seg;
@@ -529,7 +531,7 @@ dpaa_eth_sg_to_mbuf(const struct qm_fd *fd, uint32_t ifid)
DPAA_DP_LOG(DEBUG, "Received an SG frame len =%d, num_sg =%d",
first_seg->pkt_len, first_seg->nb_segs);
- dpaa_eth_packet_info(first_seg, vaddr);
+ dpaa_eth_packet_info(dpaa_intf, first_seg, GET_ANNOTATIONS(vaddr));
#ifdef RTE_LIBRTE_MEMPOOL_DEBUG
rte_mempool_check_cookies(rte_mempool_from_obj((void *)temp),
(void **)&temp, 1, 1);
@@ -540,7 +542,7 @@ dpaa_eth_sg_to_mbuf(const struct qm_fd *fd, uint32_t ifid)
}
static inline struct rte_mbuf *
-dpaa_eth_fd_to_mbuf(const struct qm_fd *fd, uint32_t ifid)
+dpaa_eth_fd_to_mbuf(struct dpaa_if *dpaa_intf, const struct qm_fd *fd)
{
struct rte_mbuf *mbuf;
struct dpaa_bp_info *bp_info = DPAA_BPID_TO_POOL_INFO(fd->bpid);
@@ -551,7 +553,7 @@ dpaa_eth_fd_to_mbuf(const struct qm_fd *fd, uint32_t ifid)
uint32_t length;
if (unlikely(format == qm_fd_sg))
- return dpaa_eth_sg_to_mbuf(fd, ifid);
+ return dpaa_eth_sg_to_mbuf(dpaa_intf, fd);
offset = (fd->opaque & DPAA_FD_OFFSET_MASK) >> DPAA_FD_OFFSET_SHIFT;
length = fd->opaque & DPAA_FD_LENGTH_MASK;
@@ -569,7 +571,7 @@ dpaa_eth_fd_to_mbuf(const struct qm_fd *fd, uint32_t ifid)
mbuf->data_len = length;
mbuf->pkt_len = length;
- mbuf->port = ifid;
+ mbuf->port = dpaa_intf->ifid;
mbuf->nb_segs = 1;
mbuf->ol_flags = 0;
mbuf->next = NULL;
@@ -578,7 +580,7 @@ dpaa_eth_fd_to_mbuf(const struct qm_fd *fd, uint32_t ifid)
rte_mempool_check_cookies(rte_mempool_from_obj((void *)mbuf),
(void **)&mbuf, 1, 1);
#endif
- dpaa_eth_packet_info(mbuf, mbuf->buf_addr);
+ dpaa_eth_packet_info(dpaa_intf, mbuf, GET_ANNOTATIONS(mbuf->buf_addr));
return mbuf;
}
@@ -670,11 +672,11 @@ dpaa_rx_cb_no_prefetch(struct qman_fq **fq, struct qm_dqrr_entry **dqrr,
}
fd = &dqrr[i]->fd;
- dpaa_intf = fq[0]->dpaa_intf;
+ dpaa_intf = fq[i]->dpaa_intf;
format = (fd->opaque & DPAA_FD_FORMAT_MASK) >>
DPAA_FD_FORMAT_SHIFT;
if (unlikely(format == qm_fd_sg)) {
- bufs[i] = dpaa_eth_sg_to_mbuf(fd, dpaa_intf->ifid);
+ bufs[i] = dpaa_eth_sg_to_mbuf(dpaa_intf, fd);
continue;
}
@@ -696,13 +698,11 @@ dpaa_rx_cb_no_prefetch(struct qman_fq **fq, struct qm_dqrr_entry **dqrr,
rte_mempool_check_cookies(rte_mempool_from_obj((void *)mbuf),
(void **)&mbuf, 1, 1);
#endif
- dpaa_eth_packet_info(mbuf, mbuf->buf_addr);
- dpaa_display_frame_info(fd, fq[0]->fqid, true);
- if (dpaa_ieee_1588) {
- annot = GET_ANNOTATIONS(mbuf->buf_addr);
- dpaa_intf->rx_timestamp =
- rte_cpu_to_be_64(annot->timestamp);
- }
+ annot = GET_ANNOTATIONS(mbuf->buf_addr);
+ dpaa_eth_packet_info(dpaa_intf, mbuf, annot);
+ dpaa_display_frame_info(fd, fq[i]->fqid, true);
+ if (unlikely(dpaa_intf->ts_enable))
+ dpaa_intf->rx_timestamp = rte_be_to_cpu_64(annot->timestamp);
}
}
@@ -720,11 +720,11 @@ dpaa_rx_cb(struct qman_fq **fq, struct qm_dqrr_entry **dqrr,
for (i = 0; i < num_bufs; i++) {
fd = &dqrr[i]->fd;
- dpaa_intf = fq[0]->dpaa_intf;
+ dpaa_intf = fq[i]->dpaa_intf;
format = (fd->opaque & DPAA_FD_FORMAT_MASK) >>
DPAA_FD_FORMAT_SHIFT;
if (unlikely(format == qm_fd_sg)) {
- bufs[i] = dpaa_eth_sg_to_mbuf(fd, dpaa_intf->ifid);
+ bufs[i] = dpaa_eth_sg_to_mbuf(dpaa_intf, fd);
continue;
}
@@ -746,13 +746,11 @@ dpaa_rx_cb(struct qman_fq **fq, struct qm_dqrr_entry **dqrr,
rte_mempool_check_cookies(rte_mempool_from_obj((void *)mbuf),
(void **)&mbuf, 1, 1);
#endif
- dpaa_eth_packet_info(mbuf, mbuf->buf_addr);
- dpaa_display_frame_info(fd, fq[0]->fqid, true);
- if (dpaa_ieee_1588) {
- annot = GET_ANNOTATIONS(mbuf->buf_addr);
- dpaa_intf->rx_timestamp =
- rte_cpu_to_be_64(annot->timestamp);
- }
+ annot = GET_ANNOTATIONS(mbuf->buf_addr);
+ dpaa_eth_packet_info(dpaa_intf, mbuf, annot);
+ dpaa_display_frame_info(fd, fq[i]->fqid, true);
+ if (unlikely(dpaa_intf->ts_enable))
+ dpaa_intf->rx_timestamp = rte_be_to_cpu_64(annot->timestamp);
}
}
@@ -787,7 +785,7 @@ dpaa_eth_queue_portal_rx(struct qman_fq *fq,
fq->qp_initialized = 1;
}
- return qman_portal_poll_rx(nb_bufs, (void **)bufs, fq->qp);
+ return qman_portal_poll_rx(nb_bufs, (void **)bufs, fq->qp, &fq->cb);
}
enum qman_cb_dqrr_result
@@ -797,11 +795,10 @@ dpaa_rx_cb_parallel(void *event,
const struct qm_dqrr_entry *dqrr,
void **bufs)
{
- u32 ifid = ((struct dpaa_if *)fq->dpaa_intf)->ifid;
struct rte_mbuf *mbuf;
struct rte_event *ev = (struct rte_event *)event;
- mbuf = dpaa_eth_fd_to_mbuf(&dqrr->fd, ifid);
+ mbuf = dpaa_eth_fd_to_mbuf(fq->dpaa_intf, &dqrr->fd);
ev->event_ptr = (void *)mbuf;
ev->flow_id = fq->ev.flow_id;
ev->sub_event_type = fq->ev.sub_event_type;
@@ -825,11 +822,10 @@ dpaa_rx_cb_atomic(void *event,
void **bufs)
{
u8 index;
- u32 ifid = ((struct dpaa_if *)fq->dpaa_intf)->ifid;
struct rte_mbuf *mbuf;
struct rte_event *ev = (struct rte_event *)event;
- mbuf = dpaa_eth_fd_to_mbuf(&dqrr->fd, ifid);
+ mbuf = dpaa_eth_fd_to_mbuf(fq->dpaa_intf, &dqrr->fd);
ev->event_ptr = (void *)mbuf;
ev->flow_id = fq->ev.flow_id;
ev->sub_event_type = fq->ev.sub_event_type;
@@ -900,7 +896,7 @@ dpaa_eth_err_queue(struct qman_fq *fq)
dpaa_display_frame_info(fd, debug_fq->fqid,
i == DPAA_DEBUG_FQ_RX_ERROR);
- mbuf = dpaa_eth_fd_to_mbuf(fd, dpaa_intf->ifid);
+ mbuf = dpaa_eth_fd_to_mbuf(dpaa_intf, fd);
rte_pktmbuf_free(mbuf);
qman_dqrr_consume(debug_fq, dq);
} while (debug_fq->flags & QMAN_FQ_STATE_VDQCR);
@@ -908,13 +904,12 @@ dpaa_eth_err_queue(struct qman_fq *fq)
}
#endif
-uint16_t dpaa_eth_queue_rx(void *q,
- struct rte_mbuf **bufs,
- uint16_t nb_bufs)
+uint16_t
+dpaa_eth_queue_rx(void *q, struct rte_mbuf **bufs, uint16_t nb_bufs)
{
struct qman_fq *fq = q;
struct qm_dqrr_entry *dq;
- uint32_t num_rx = 0, ifid = ((struct dpaa_if *)fq->dpaa_intf)->ifid;
+ uint32_t num_rx = 0;
int num_rx_bufs, ret;
uint32_t vdqcr_flags = 0;
struct annotations_t *annot;
@@ -959,11 +954,11 @@ uint16_t dpaa_eth_queue_rx(void *q,
dq = qman_dequeue(fq);
if (!dq)
continue;
- bufs[num_rx++] = dpaa_eth_fd_to_mbuf(&dq->fd, ifid);
+ bufs[num_rx++] = dpaa_eth_fd_to_mbuf(dpaa_intf, &dq->fd);
dpaa_display_frame_info(&dq->fd, fq->fqid, true);
- if (dpaa_ieee_1588) {
+ if (unlikely(dpaa_intf->ts_enable)) {
annot = GET_ANNOTATIONS(bufs[num_rx - 1]->buf_addr);
- dpaa_intf->rx_timestamp = rte_cpu_to_be_64(annot->timestamp);
+ dpaa_intf->rx_timestamp = rte_be_to_cpu_64(annot->timestamp);
}
qman_dqrr_consume(fq, dq);
} while (fq->flags & QMAN_FQ_STATE_VDQCR);
@@ -1314,10 +1309,9 @@ dpaa_eth_queue_tx(void *q, struct rte_mbuf **bufs, uint16_t nb_bufs)
DPAA_DP_LOG(DEBUG, "Transmitting %d buffers on queue: %p", nb_bufs, q);
- if (dpaa_ieee_1588) {
+ if (unlikely(dpaa_intf->ts_enable)) {
dpaa_intf->next_tx_conf_queue = fq_txconf;
dpaa_eth_tx_conf(fq_txconf);
- dpaa_intf->tx_timestamp = 0;
}
while (nb_bufs) {
@@ -1326,7 +1320,7 @@ dpaa_eth_queue_tx(void *q, struct rte_mbuf **bufs, uint16_t nb_bufs)
for (loop = 0; loop < frames_to_send; loop++) {
mbuf = *(bufs++);
fd_arr[loop].cmd = 0;
- if (dpaa_ieee_1588) {
+ if (unlikely(dpaa_intf->ts_enable)) {
fd_arr[loop].cmd |= DPAA_FD_CMD_FCO |
qman_fq_fqid(fq_txconf);
fd_arr[loop].cmd |= DPAA_FD_CMD_RPD |
@@ -1481,8 +1475,7 @@ dpaa_eth_tx_conf(void *q)
if (mbuf->ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST) {
annot = GET_ANNOTATIONS(mbuf->buf_addr);
- dpaa_intf->tx_timestamp =
- rte_cpu_to_be_64(annot->timestamp);
+ dpaa_intf->tx_timestamp = rte_be_to_cpu_64(annot->timestamp);
}
dpaa_display_frame_info(&dq->fd, fq->fqid, true);
qman_dqrr_consume(fq, dq);
diff --git a/drivers/net/dpaa/dpaa_rxtx.h b/drivers/net/dpaa/dpaa_rxtx.h
index edb29788fb..233339a488 100644
--- a/drivers/net/dpaa/dpaa_rxtx.h
+++ b/drivers/net/dpaa/dpaa_rxtx.h
@@ -239,7 +239,7 @@ struct __rte_packed_begin dpaa_eth_parse_results_t {
struct annotations_t {
uint8_t reserved[DEFAULT_RX_ICEOF];
struct dpaa_eth_parse_results_t parse; /**< Pointer to Parsed result*/
- uint64_t timestamp;
+ rte_be64_t timestamp;
uint64_t hash; /**< Hash Result */
};
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 3/5] bus/dpaa: Disable qman Invalid Enqueue State interrupt
2025-10-07 5:00 [PATCH 0/5] DPAA specific changes Gagandeep Singh
2025-10-07 5:00 ` [PATCH 1/5] bus/dpaa: add FQ shutdown and improve logging Gagandeep Singh
2025-10-07 5:00 ` [PATCH 2/5] net/dpaa: Support IEEE1588 by timesync API Gagandeep Singh
@ 2025-10-07 5:00 ` Gagandeep Singh
2025-10-07 5:00 ` [PATCH 4/5] bus/dpaa: Set max push RXQ number Gagandeep Singh
` (2 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Gagandeep Singh @ 2025-10-07 5:00 UTC (permalink / raw)
To: dev, Hemant Agrawal, Sachin Saxena; +Cc: Jun Yang
From: Jun Yang <jun.yang@nxp.com>
ShareMAC port is still alive after dpdk process quits but RXQ setup
in dpdk process is in invalid state. If high loading ingress traffic
hits the FMan PCD then it's en-queued to the RXQ to generate frequent
interrupts. This causes system stuck.
User can disable this kind of interrupt by env to avoid this issue:
export DPAA_QMAN_IESR_ISR_DISABLE=1
Signed-off-by: Jun Yang <jun.yang@nxp.com>
---
drivers/bus/dpaa/base/qbman/qman_driver.c | 27 ++++++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/bus/dpaa/base/qbman/qman_driver.c b/drivers/bus/dpaa/base/qbman/qman_driver.c
index cdce6b777b..3a202c6b77 100644
--- a/drivers/bus/dpaa/base/qbman/qman_driver.c
+++ b/drivers/bus/dpaa/base/qbman/qman_driver.c
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
*
* Copyright 2008-2016 Freescale Semiconductor Inc.
- * Copyright 2017-2022 NXP
+ * Copyright 2017-2022, 2025 NXP
*
*/
@@ -32,6 +32,29 @@ static __thread struct dpaa_ioctl_portal_map map = {
.type = dpaa_portal_qman
};
+#define REG_ERR_IER 0x0e04
+#define QM_EIRQ_IESI 0x00000004
+
+static void dpaa_qm_iesr_irq_control(void)
+{
+ char *env = getenv("DPAA_QMAN_IESR_ISR_DISABLE");
+ uint32_t val;
+
+ if (!qman_ccsr_map) {
+ pr_err("qman CCSR not mapped!\n");
+ return;
+ }
+
+ val = in_be32((void *)((u64)qman_ccsr_map + REG_ERR_IER));
+
+ if (!env || atoi(env) == 0)
+ val = val | QM_EIRQ_IESI;
+ else
+ val = val & (~((uint32_t)QM_EIRQ_IESI));
+
+ out_be32((void *)((u64)qman_ccsr_map + REG_ERR_IER), val);
+}
+
u16 dpaa_get_qm_channel_caam(void)
{
return qm_channel_caam;
@@ -343,6 +366,8 @@ int qman_global_init(void)
return -EINVAL;
}
+ dpaa_qm_iesr_irq_control();
+
clk = of_get_property(dt_node, "clock-frequency", NULL);
if (!clk)
pr_warn("Can't find Qman clock frequency\n");
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 4/5] bus/dpaa: Set max push RXQ number
2025-10-07 5:00 [PATCH 0/5] DPAA specific changes Gagandeep Singh
` (2 preceding siblings ...)
2025-10-07 5:00 ` [PATCH 3/5] bus/dpaa: Disable qman Invalid Enqueue State interrupt Gagandeep Singh
@ 2025-10-07 5:00 ` Gagandeep Singh
2025-10-07 5:00 ` [PATCH 5/5] net/dpaa: Fix coverity issue Gagandeep Singh
2025-10-08 4:35 ` [PATCH v2 0/5] DPAA specific changes Gagandeep Singh
5 siblings, 0 replies; 12+ messages in thread
From: Gagandeep Singh @ 2025-10-07 5:00 UTC (permalink / raw)
To: dev, Hemant Agrawal, Sachin Saxena; +Cc: Jun Yang
From: Jun Yang <jun.yang@nxp.com>
Max push queue number is bus level number affecting all dpaa devices.
Move the configuration from PMD driver to bus driver.
Signed-off-by: Jun Yang <jun.yang@nxp.com>
---
drivers/bus/dpaa/bus_dpaa_driver.h | 6 ++++
drivers/bus/dpaa/dpaa_bus.c | 51 ++++++++++++++++++++++++++++++
drivers/net/dpaa/dpaa_ethdev.c | 51 ++++++++----------------------
3 files changed, 70 insertions(+), 38 deletions(-)
diff --git a/drivers/bus/dpaa/bus_dpaa_driver.h b/drivers/bus/dpaa/bus_dpaa_driver.h
index 976f356699..cca0543432 100644
--- a/drivers/bus/dpaa/bus_dpaa_driver.h
+++ b/drivers/bus/dpaa/bus_dpaa_driver.h
@@ -249,6 +249,12 @@ struct fm_eth_port_cfg *dpaa_get_eth_port_cfg(int dev_id);
__rte_internal
uint32_t dpaa_soc_ver(void);
+__rte_internal
+int dpaa_push_queue_num_update(void);
+
+__rte_internal
+uint16_t dpaa_push_queue_max_num(void);
+
#ifdef __cplusplus
}
#endif
diff --git a/drivers/bus/dpaa/dpaa_bus.c b/drivers/bus/dpaa/dpaa_bus.c
index 1a35aa52df..d9830b68ca 100644
--- a/drivers/bus/dpaa/dpaa_bus.c
+++ b/drivers/bus/dpaa/dpaa_bus.c
@@ -50,6 +50,13 @@
#define DPAA_SVR_MASK 0xffff0000
#define RTE_PRIORITY_102 102
+#define DPAA_PUSH_RXQ_NUM_ARG "dpaa_push_rxq_num"
+/* At present we allow up to 4 push mode queues as default - as each of
+ * this queue need dedicated portal and we are short of portals.
+ */
+#define DPAA_MAX_PUSH_MODE_QUEUE 8
+#define DPAA_DEFAULT_PUSH_MODE_QUEUE 4
+
struct rte_dpaa_bus {
struct rte_bus bus;
TAILQ_HEAD(, rte_dpaa_device) device_list;
@@ -57,6 +64,8 @@ struct rte_dpaa_bus {
int device_count;
int detected;
uint32_t svr_ver;
+ uint16_t max_push_rxq_num;
+ RTE_ATOMIC(uint16_t) push_rxq_num;
};
static struct rte_dpaa_bus rte_dpaa_bus;
@@ -91,6 +100,34 @@ dpaa_get_eth_port_cfg(int dev_id)
return &dpaa_netcfg->port_cfg[dev_id];
}
+RTE_EXPORT_INTERNAL_SYMBOL(dpaa_push_queue_num_update)
+int
+dpaa_push_queue_num_update(void)
+{
+ int ret = false;
+ uint16_t current, new_val;
+
+ current = rte_atomic_load_explicit(&rte_dpaa_bus.push_rxq_num,
+ rte_memory_order_acquire);
+ if (current < rte_dpaa_bus.max_push_rxq_num) {
+ new_val = current + 1;
+ if (rte_atomic_compare_exchange_strong_explicit(&rte_dpaa_bus.push_rxq_num,
+ ¤t, new_val,
+ rte_memory_order_release,
+ rte_memory_order_acquire))
+ ret = true;
+ }
+
+ return ret;
+}
+
+RTE_EXPORT_INTERNAL_SYMBOL(dpaa_push_queue_max_num)
+uint16_t
+dpaa_push_queue_max_num(void)
+{
+ return rte_dpaa_bus.max_push_rxq_num;
+}
+
static int
compare_dpaa_devices(struct rte_dpaa_device *dev1,
struct rte_dpaa_device *dev2)
@@ -681,6 +718,7 @@ rte_dpaa_bus_probe(void)
uint32_t svr_ver;
int probe_all = rte_dpaa_bus.bus.conf.scan_mode != RTE_BUS_SCAN_ALLOWLIST;
static int process_once;
+ char *penv;
/* If DPAA bus is not present nothing needs to be done */
if (!rte_dpaa_bus.detected)
@@ -709,6 +747,18 @@ rte_dpaa_bus_probe(void)
rte_dpaa_bus.svr_ver);
}
+ /* Disabling the default push mode for LS1043A */
+ if (rte_dpaa_bus.svr_ver == SVR_LS1043A_FAMILY) {
+ rte_dpaa_bus.max_push_rxq_num = 0;
+ return 0;
+ }
+
+ penv = getenv("DPAA_PUSH_QUEUES_NUMBER");
+ if (penv)
+ rte_dpaa_bus.max_push_rxq_num = atoi(penv);
+ if (rte_dpaa_bus.max_push_rxq_num > DPAA_MAX_PUSH_MODE_QUEUE)
+ rte_dpaa_bus.max_push_rxq_num = DPAA_MAX_PUSH_MODE_QUEUE;
+
/* Device list creation is only done once */
if (!process_once) {
rte_dpaa_bus_dev_build();
@@ -947,6 +997,7 @@ static struct rte_dpaa_bus rte_dpaa_bus = {
.dev_iterate = dpaa_bus_dev_iterate,
.cleanup = dpaa_bus_cleanup,
},
+ .max_push_rxq_num = DPAA_DEFAULT_PUSH_MODE_QUEUE,
.device_list = TAILQ_HEAD_INITIALIZER(rte_dpaa_bus.device_list),
.driver_list = TAILQ_HEAD_INITIALIZER(rte_dpaa_bus.driver_list),
.device_count = 0,
diff --git a/drivers/net/dpaa/dpaa_ethdev.c b/drivers/net/dpaa/dpaa_ethdev.c
index 43aab98339..0baf5c03fa 100644
--- a/drivers/net/dpaa/dpaa_ethdev.c
+++ b/drivers/net/dpaa/dpaa_ethdev.c
@@ -89,16 +89,6 @@ static int fmc_q = 1; /* Indicates the use of static fmc for distribution */
static int default_q; /* use default queue - FMC is not executed*/
bool dpaa_enable_recv_err_pkts; /* Enable main queue to receive error packets */
-/* At present we only allow up to 4 push mode queues as default - as each of
- * this queue need dedicated portal and we are short of portals.
- */
-#define DPAA_MAX_PUSH_MODE_QUEUE 8
-#define DPAA_DEFAULT_PUSH_MODE_QUEUE 4
-
-static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE;
-static int dpaa_push_queue_idx; /* Queue index which are in push mode*/
-
-
/* Per RX FQ Taildrop in frame count */
static unsigned int td_threshold = CGR_RX_PERFQ_THRESH;
@@ -1113,7 +1103,7 @@ int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx];
struct qm_mcc_initfq opts = {0};
u32 ch_id, flags = 0;
- int ret;
+ int ret, set_push_rxq = false;
u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
uint32_t max_rx_pktlen;
@@ -1214,12 +1204,12 @@ int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name,
fman_if_get_sg_enable(fif), max_rx_pktlen);
/* checking if push mode only, no error check for now */
- if (!rxq->is_static &&
- dpaa_push_mode_max_queue > dpaa_push_queue_idx) {
+ if (!rxq->is_static)
+ set_push_rxq = dpaa_push_queue_num_update();
+ if (set_push_rxq) {
struct qman_portal *qp;
int q_fd;
- dpaa_push_queue_idx++;
opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK |
QM_FQCTRL_CTXASTASHING |
@@ -1269,7 +1259,7 @@ int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
qp = fsl_qman_fq_portal_create(&q_fd);
if (!qp) {
DPAA_PMD_ERR("Unable to alloc fq portal");
- return -1;
+ return -EIO;
}
rxq->qp = qp;
@@ -1279,19 +1269,19 @@ int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
struct rte_device *rdev = dev->device;
dpaa_dev = container_of(rdev, struct rte_dpaa_device,
- device);
+ device);
dev->intr_handle = dpaa_dev->intr_handle;
if (rte_intr_vec_list_alloc(dev->intr_handle,
- NULL, dpaa_push_mode_max_queue)) {
+ NULL, dpaa_push_queue_max_num())) {
DPAA_PMD_ERR("intr_vec alloc failed");
return -ENOMEM;
}
if (rte_intr_nb_efd_set(dev->intr_handle,
- dpaa_push_mode_max_queue))
+ dpaa_push_queue_max_num()))
return -rte_errno;
if (rte_intr_max_intr_set(dev->intr_handle,
- dpaa_push_mode_max_queue))
+ dpaa_push_queue_max_num()))
return -rte_errno;
}
@@ -1339,9 +1329,8 @@ int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
RTE_EXPORT_INTERNAL_SYMBOL(dpaa_eth_eventq_attach)
int
dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
- int eth_rx_queue_id,
- u16 ch_id,
- const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
+ int eth_rx_queue_id, u16 ch_id,
+ const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
{
int ret;
u32 flags = 0;
@@ -1349,10 +1338,10 @@ dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
struct qm_mcc_initfq opts = {0};
- if (dpaa_push_mode_max_queue) {
+ if (dpaa_push_queue_max_num() > 0) {
DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible");
DPAA_PMD_WARN("PUSH mode already enabled for first %d queues.",
- dpaa_push_mode_max_queue);
+ dpaa_push_queue_max_num());
DPAA_PMD_WARN("To disable set DPAA_PUSH_QUEUES_NUMBER to 0");
}
@@ -2581,20 +2570,6 @@ rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv,
}
}
- /* disabling the default push mode for LS1043 */
- if (dpaa_soc_ver() == SVR_LS1043A_FAMILY)
- dpaa_push_mode_max_queue = 0;
-
- /* if push mode queues to be enabled. Currently we are allowing
- * only one queue per thread.
- */
- if (getenv("DPAA_PUSH_QUEUES_NUMBER")) {
- dpaa_push_mode_max_queue =
- atoi(getenv("DPAA_PUSH_QUEUES_NUMBER"));
- if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE)
- dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE;
- }
-
is_global_init = 1;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 5/5] net/dpaa: Fix coverity issue
2025-10-07 5:00 [PATCH 0/5] DPAA specific changes Gagandeep Singh
` (3 preceding siblings ...)
2025-10-07 5:00 ` [PATCH 4/5] bus/dpaa: Set max push RXQ number Gagandeep Singh
@ 2025-10-07 5:00 ` Gagandeep Singh
2025-10-08 4:35 ` [PATCH v2 0/5] DPAA specific changes Gagandeep Singh
5 siblings, 0 replies; 12+ messages in thread
From: Gagandeep Singh @ 2025-10-07 5:00 UTC (permalink / raw)
To: dev, Hemant Agrawal, Sachin Saxena; +Cc: Vanshika Shukla
From: Vanshika Shukla <vanshika.shukla@nxp.com>
Fix Resource leak CID:362787 issue reported by external coverity tool.
Signed-off-by: Vanshika Shukla <vanshika.shukla@nxp.com>
---
drivers/net/dpaa/dpaa_flow.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/dpaa/dpaa_flow.c b/drivers/net/dpaa/dpaa_flow.c
index 2a22b23c8f..417b9b6fbb 100644
--- a/drivers/net/dpaa/dpaa_flow.c
+++ b/drivers/net/dpaa/dpaa_flow.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright 2017-2019,2021-2024 NXP
+ * Copyright 2017-2019,2021-2025 NXP
*/
/* System headers */
@@ -889,9 +889,9 @@ int dpaa_fm_init(void)
/* FM PCD Enable */
ret = fm_pcd_enable(pcd_handle);
if (ret) {
- fm_close(fman_handle);
- fm_pcd_close(pcd_handle);
DPAA_PMD_ERR("fm_pcd_enable: Failed");
+ fm_pcd_close(pcd_handle);
+ fm_close(fman_handle);
return -1;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 0/5] DPAA specific changes
2025-10-07 5:00 [PATCH 0/5] DPAA specific changes Gagandeep Singh
` (4 preceding siblings ...)
2025-10-07 5:00 ` [PATCH 5/5] net/dpaa: Fix coverity issue Gagandeep Singh
@ 2025-10-08 4:35 ` Gagandeep Singh
2025-10-08 4:35 ` [PATCH v2 1/5] bus/dpaa: add FQ shutdown and improve logging Gagandeep Singh
` (4 more replies)
5 siblings, 5 replies; 12+ messages in thread
From: Gagandeep Singh @ 2025-10-08 4:35 UTC (permalink / raw)
To: dev; +Cc: hemant.agrawal
This series support timesync APIs, improves
queue reset logic and include minor fixes.
v2 change log:
- fix 32 bit compilation
Gagandeep Singh (1):
bus/dpaa: add FQ shutdown and improve logging
Jun Yang (3):
net/dpaa: Support IEEE1588 by timesync API
bus/dpaa: Disable qman Invalid Enqueue State interrupt
bus/dpaa: Set max push RXQ number
Vanshika Shukla (1):
net/dpaa: Fix coverity issue
doc/guides/nics/dpaa.rst | 3 -
drivers/bus/dpaa/base/qbman/qman.c | 412 +++++++++++++++++++---
drivers/bus/dpaa/base/qbman/qman_driver.c | 27 +-
drivers/bus/dpaa/bus_dpaa_driver.h | 6 +
drivers/bus/dpaa/dpaa_bus.c | 51 +++
drivers/bus/dpaa/include/fsl_qman.h | 8 +-
drivers/common/dpaax/dpaax_ptp.h | 95 +++++
drivers/net/dpaa/dpaa_ethdev.c | 69 ++--
drivers/net/dpaa/dpaa_ethdev.h | 13 +-
drivers/net/dpaa/dpaa_flow.c | 6 +-
drivers/net/dpaa/dpaa_ptp.c | 50 ++-
drivers/net/dpaa/dpaa_rxtx.c | 93 +++--
drivers/net/dpaa/dpaa_rxtx.h | 2 +-
13 files changed, 672 insertions(+), 163 deletions(-)
create mode 100644 drivers/common/dpaax/dpaax_ptp.h
--
2.25.1
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v2 1/5] bus/dpaa: add FQ shutdown and improve logging
2025-10-08 4:35 ` [PATCH v2 0/5] DPAA specific changes Gagandeep Singh
@ 2025-10-08 4:35 ` Gagandeep Singh
2025-10-08 4:35 ` [PATCH v2 2/5] net/dpaa: Support IEEE1588 by timesync API Gagandeep Singh
` (3 subsequent siblings)
4 siblings, 0 replies; 12+ messages in thread
From: Gagandeep Singh @ 2025-10-08 4:35 UTC (permalink / raw)
To: dev, Hemant Agrawal, Sachin Saxena
adding a FQ shutdown functionality to ensure proper cleanup of
frame queues during queue setup. This helps reset the
queues reliably and prevents potential resource leaks or
stale state issues.
Additionally, update logging to use DPAA_BUS_ERR instead
of pr_err for better consistency and clarity in error
reporting within the DPAA bus subsystem.
These changes enhance maintainability and improve
debugging experience.
Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
---
drivers/bus/dpaa/base/qbman/qman.c | 394 +++++++++++++++++++++++++---
drivers/bus/dpaa/include/fsl_qman.h | 3 +
drivers/net/dpaa/dpaa_ethdev.c | 3 +
3 files changed, 369 insertions(+), 31 deletions(-)
diff --git a/drivers/bus/dpaa/base/qbman/qman.c b/drivers/bus/dpaa/base/qbman/qman.c
index 60087c55a1..6ce3690366 100644
--- a/drivers/bus/dpaa/base/qbman/qman.c
+++ b/drivers/bus/dpaa/base/qbman/qman.c
@@ -10,7 +10,8 @@
#include <bus_dpaa_driver.h>
#include <rte_eventdev.h>
#include <rte_byteorder.h>
-
+#include <rte_dpaa_logs.h>
+#include <eal_export.h>
#include <dpaa_bits.h>
/* Compilation constants */
@@ -137,7 +138,7 @@ static inline int table_push_fq(struct qman_portal *p, struct qman_fq *fq)
int ret = fqtree_push(&p->retire_table, fq);
if (ret)
- pr_err("ERROR: double FQ-retirement %d\n", fq->fqid);
+ DPAA_BUS_ERR("ERROR: double FQ-retirement %d", fq->fqid);
return ret;
}
@@ -161,7 +162,7 @@ int qman_setup_fq_lookup_table(size_t num_entries)
/* Allocate 1 more entry since the first entry is not used */
qman_fq_lookup_table = vmalloc((num_entries * sizeof(void *)));
if (!qman_fq_lookup_table) {
- pr_err("QMan: Could not allocate fq lookup table\n");
+ DPAA_BUS_ERR("QMan: Could not allocate fq lookup table");
return -ENOMEM;
}
memset(qman_fq_lookup_table, 0, num_entries * sizeof(void *));
@@ -349,7 +350,8 @@ static int drain_mr_fqrni(struct qm_portal *p)
}
if ((msg->ern.verb & QM_MR_VERB_TYPE_MASK) != QM_MR_VERB_FQRNI) {
/* We aren't draining anything but FQRNIs */
- pr_err("Found verb 0x%x in MR\n", msg->ern.verb);
+ DPAA_BUS_ERR("Found verb 0x%x and after mask = 0x%x in MR",
+ msg->ern.verb, msg->ern.verb & QM_MR_VERB_TYPE_MASK);
return -1;
}
qm_mr_next(p);
@@ -423,11 +425,11 @@ static inline void qm_eqcr_finish(struct qm_portal *portal)
DPAA_ASSERT(!eqcr->busy);
#endif
if (pi != EQCR_PTR2IDX(eqcr->cursor))
- pr_crit("losing uncommitted EQCR entries\n");
+ DPAA_BUS_ERR("losing uncommitted EQCR entries");
if (ci != eqcr->ci)
- pr_crit("missing existing EQCR completions\n");
+ DPAA_BUS_ERR("missing existing EQCR completions");
if (eqcr->ci != EQCR_PTR2IDX(eqcr->cursor))
- pr_crit("EQCR destroyed unquiesced\n");
+ DPAA_BUS_ERR("EQCR destroyed unquiesced");
}
static inline int qm_dqrr_init(struct qm_portal *portal,
@@ -515,6 +517,7 @@ qman_init_portal(struct qman_portal *portal,
int ret;
u32 isdr;
+
p = &portal->p;
if (!c)
@@ -540,30 +543,68 @@ qman_init_portal(struct qman_portal *portal,
*/
if (qm_eqcr_init(p, qm_eqcr_pvb,
portal->use_eqcr_ci_stashing, 1)) {
- pr_err("Qman EQCR initialisation failed\n");
+ DPAA_BUS_ERR("Qman EQCR initialisation failed");
+ goto fail_eqcr;
+ }
+ if (qm_dqrr_init(p, c, qm_dqrr_dpush, qm_dqrr_pvb,
+ qm_dqrr_cdc, DQRR_MAXFILL)) {
+ DPAA_BUS_ERR("Qman DQRR initialisation failed");
+ goto fail_dqrr;
+ }
+ if (qm_mr_init(p, qm_mr_pvb, qm_mr_cci)) {
+ DPAA_BUS_ERR("Qman MR initialisation failed");
+ goto fail_mr;
+ }
+ if (qm_mc_init(p)) {
+ DPAA_BUS_ERR("Qman MC initialisation failed");
+ goto fail_mc;
+ }
+
+ /* Reset portal before use */
+ DPAA_BUS_DEBUG("Reset portal = %p", p);
+ qm_dqrr_sdqcr_set(p, 0);
+ qm_eqcr_cce_update(p);
+ qm_eqcr_cce_update(p);
+ qm_mc_finish(p);
+ qm_mr_finish(p);
+ qm_dqrr_finish(p);
+ qm_eqcr_finish(p);
+
+ p->addr.ce = c->addr_virt[DPAA_PORTAL_CE];
+ p->addr.ci = c->addr_virt[DPAA_PORTAL_CI];
+ /*
+ * If CI-stashing is used, the current defaults use a threshold of 3,
+ * and stash with high-than-DQRR priority.
+ */
+ if (qm_eqcr_init(p, qm_eqcr_pvb,
+ portal->use_eqcr_ci_stashing, 1)) {
+ DPAA_BUS_ERR("Qman EQCR initialisation failed");
goto fail_eqcr;
}
if (qm_dqrr_init(p, c, qm_dqrr_dpush, qm_dqrr_pvb,
qm_dqrr_cdc, DQRR_MAXFILL)) {
- pr_err("Qman DQRR initialisation failed\n");
+ DPAA_BUS_ERR("Qman DQRR initialisation failed");
goto fail_dqrr;
}
if (qm_mr_init(p, qm_mr_pvb, qm_mr_cci)) {
- pr_err("Qman MR initialisation failed\n");
+ DPAA_BUS_ERR("Qman MR initialisation failed");
goto fail_mr;
}
if (qm_mc_init(p)) {
- pr_err("Qman MC initialisation failed\n");
+ DPAA_BUS_ERR("Qman MC initialisation failed");
goto fail_mc;
}
+
/* static interrupt-gating controls */
qm_dqrr_set_ithresh(p, 0);
qm_mr_set_ithresh(p, 0);
qm_isr_set_iperiod(p, 0);
portal->cgrs = kmalloc(2 * sizeof(*cgrs), GFP_KERNEL);
- if (!portal->cgrs)
+ if (!portal->cgrs) {
+ DPAA_BUS_ERR("CGRS allocation fails");
goto fail_cgrs;
+ }
/* initial snapshot is no-depletion */
qman_cgrs_init(&portal->cgrs[1]);
if (cgrs)
@@ -580,6 +621,7 @@ qman_init_portal(struct qman_portal *portal,
portal->dqrr_disable_ref = 0;
portal->cb_dc_ern = NULL;
sprintf(buf, "qportal-%d", c->channel);
+ DPAA_BUS_DEBUG("PORTAL ID = %d and %p", c->channel, p);
dpa_rbtree_init(&portal->retire_table);
isdr = 0xffffffff;
qm_isr_disable_write(p, isdr);
@@ -589,7 +631,7 @@ qman_init_portal(struct qman_portal *portal,
snprintf(portal->irqname, MAX_IRQNAME, IRQNAME, c->cpu);
if (request_irq(c->irq, portal_isr, 0, portal->irqname,
portal)) {
- pr_err("request_irq() failed\n");
+ DPAA_BUS_ERR("request_irq() failed");
goto fail_irq;
}
@@ -598,19 +640,22 @@ qman_init_portal(struct qman_portal *portal,
qm_isr_disable_write(p, isdr);
ret = qm_eqcr_get_fill(p);
if (ret) {
- pr_err("Qman EQCR unclean\n");
+ DPAA_BUS_ERR("Qman EQCR unclean");
goto fail_eqcr_empty;
}
isdr &= ~(QM_PIRQ_DQRI | QM_PIRQ_MRI);
qm_isr_disable_write(p, isdr);
if (qm_dqrr_current(p)) {
- pr_err("Qman DQRR unclean\n");
+ DPAA_BUS_ERR("Qman DQRR unclean");
qm_dqrr_cdc_consume_n(p, 0xffff);
}
if (qm_mr_current(p) && drain_mr_fqrni(p)) {
/* special handling, drain just in case it's a few FQRNIs */
- if (drain_mr_fqrni(p))
+ DPAA_BUS_ERR("Draining MR FQRNI");
+ if (drain_mr_fqrni(p)) {
+ DPAA_BUS_ERR("Draining MR FQRNI fails");
goto fail_dqrr_mr_empty;
+ }
}
/* Success */
portal->config = c;
@@ -652,7 +697,7 @@ qman_alloc_global_portal(struct qm_portal_config *q_pcfg)
return &global_portals[i];
}
}
- pr_err("No portal available (%x)\n", MAX_GLOBAL_PORTALS);
+ DPAA_BUS_ERR("No portal available (%x)", MAX_GLOBAL_PORTALS);
return NULL;
}
@@ -702,6 +747,7 @@ void qman_destroy_portal(struct qman_portal *qm)
{
const struct qm_portal_config *pcfg;
+ DPAA_BUS_DEBUG("In destroy portal = %p", &qm->p);
/* Stop dequeues on the portal */
qm_dqrr_sdqcr_set(&qm->p, 0);
@@ -1488,7 +1534,7 @@ int qman_create_fq(u32 fqid, u32 flags, struct qman_fq *fq)
cpu_relax();
DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCC_VERB_QUERYFQ);
if (mcr->result != QM_MCR_RESULT_OK) {
- pr_err("QUERYFQ failed: %s\n", mcr_result_str(mcr->result));
+ DPAA_BUS_ERR("QUERYFQ failed: %s", mcr_result_str(mcr->result));
goto err;
}
fqd = mcr->queryfq.fqd;
@@ -1500,7 +1546,7 @@ int qman_create_fq(u32 fqid, u32 flags, struct qman_fq *fq)
cpu_relax();
DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCC_VERB_QUERYFQ_NP);
if (mcr->result != QM_MCR_RESULT_OK) {
- pr_err("QUERYFQ_NP failed: %s\n", mcr_result_str(mcr->result));
+ DPAA_BUS_ERR("QUERYFQ_NP failed: %s", mcr_result_str(mcr->result));
goto err;
}
np = mcr->queryfq_np;
@@ -2026,7 +2072,7 @@ int qman_query_wq(u8 query_dedicated, struct qm_mcr_querywq *wq)
wq->wq_len[i] = be32_to_cpu(mcr->querywq.wq_len[i]);
}
if (res != QM_MCR_RESULT_OK) {
- pr_err("QUERYWQ failed: %s\n", mcr_result_str(res));
+ DPAA_BUS_ERR("QUERYWQ failed: %s", mcr_result_str(res));
return -EIO;
}
return 0;
@@ -2053,7 +2099,7 @@ int qman_testwrite_cgr(struct qman_cgr *cgr, u64 i_bcnt,
if (res == QM_MCR_RESULT_OK)
*result = mcr->cgrtestwrite;
if (res != QM_MCR_RESULT_OK) {
- pr_err("CGR TEST WRITE failed: %s\n", mcr_result_str(res));
+ DPAA_BUS_ERR("CGR TEST WRITE failed: %s", mcr_result_str(res));
return -EIO;
}
return 0;
@@ -2077,7 +2123,7 @@ int qman_query_cgr(struct qman_cgr *cgr, struct qm_mcr_querycgr *cgrd)
if (res == QM_MCR_RESULT_OK)
*cgrd = mcr->querycgr;
if (res != QM_MCR_RESULT_OK) {
- pr_err("QUERY_CGR failed: %s\n", mcr_result_str(res));
+ DPAA_BUS_ERR("QUERY_CGR failed: %s", mcr_result_str(res));
return -EIO;
}
cgrd->cgr.wr_parm_g.word =
@@ -2111,7 +2157,7 @@ int qman_query_congestion(struct qm_mcr_querycongestion *congestion)
if (res == QM_MCR_RESULT_OK)
*congestion = mcr->querycongestion;
if (res != QM_MCR_RESULT_OK) {
- pr_err("QUERY_CONGESTION failed: %s\n", mcr_result_str(res));
+ DPAA_BUS_ERR("QUERY_CONGESTION failed: %s", mcr_result_str(res));
return -EIO;
}
for (i = 0; i < ARRAY_SIZE(congestion->state.state); i++)
@@ -2660,6 +2706,287 @@ int qman_delete_cgr(struct qman_cgr *cgr)
return ret;
}
+#define GENMASK(h, l) \
+ (((~0U) >> (sizeof(unsigned int) * 8 - ((h) - (l) + 1))) << (l))
+
+/* 'fqid' is a 24-bit field in every h/w descriptor */
+#define QM_FQID_MASK GENMASK(23, 0)
+#define qm_fqid_set(p, v) ((p)->fqid = cpu_to_be32((v) & QM_FQID_MASK))
+#define qm_fqid_get(p) (be32_to_cpu((p)->fqid) & QM_FQID_MASK)
+
+static int
+_qm_mr_consume_and_match_verb(struct qm_portal *p, int v)
+{
+ const struct qm_mr_entry *msg;
+ int found = 0;
+
+ qm_mr_pvb_update(p);
+ msg = qm_mr_current(p);
+ while (msg) {
+ if ((msg->ern.verb & QM_MR_VERB_TYPE_MASK) == v)
+ found = 1;
+ qm_mr_next(p);
+ qm_mr_cci_consume_to_current(p);
+ qm_mr_pvb_update(p);
+ msg = qm_mr_current(p);
+ }
+ return found;
+}
+
+static int
+_qm_dqrr_consume_and_match(struct qm_portal *p, u32 fqid, int s,
+ bool wait)
+{
+ const struct qm_dqrr_entry *dqrr;
+ int found = 0;
+
+ do {
+ qm_dqrr_pvb_update(p);
+ dqrr = qm_dqrr_current(p);
+ if (!dqrr)
+ cpu_relax();
+ } while (wait && !dqrr);
+
+ while (dqrr) {
+ if (qm_fqid_get(dqrr) == fqid && (dqrr->stat & s))
+ found = 1;
+
+ qm_dqrr_cdc_consume_1ptr(p, dqrr, 0);
+ qm_dqrr_pvb_update(p);
+ qm_dqrr_next(p);
+ dqrr = qm_dqrr_current(p);
+ }
+ return found;
+}
+
+#define QM_MCR_TIMEOUT 10000 /* us */
+
+static inline int
+qm_mc_result_timeout(struct qm_portal *portal,
+ struct qm_mc_result **mcr)
+{
+ int timeout = QM_MCR_TIMEOUT;
+
+ do {
+ *mcr = qm_mc_result(portal);
+ if (*mcr)
+ break;
+ usleep(1);
+ } while (--timeout);
+
+ return timeout;
+}
+
+#define qm_mr_drain(p, V) \
+ _qm_mr_consume_and_match_verb(p, QM_MR_VERB_##V)
+
+#define qm_dqrr_drain(p, f, S) \
+ _qm_dqrr_consume_and_match(p, f, QM_DQRR_STAT_##S, false)
+
+#define qm_dqrr_drain_wait(p, f, S) \
+ _qm_dqrr_consume_and_match(p, f, QM_DQRR_STAT_##S, true)
+
+#define qm_dqrr_drain_nomatch(p) \
+ _qm_dqrr_consume_and_match(p, 0, 0, false)
+
+RTE_EXPORT_INTERNAL_SYMBOL(qman_shutdown_fq_new)
+int
+qman_shutdown_fq_new(u32 fqid)
+{
+ struct qman_portal *p;
+ struct qm_mc_command *mcc;
+ struct qm_mc_result *mcr;
+ int orl_empty, drain = 0, ret = 0;
+ u32 res;
+ u8 state;
+ u32 channel, wq;
+ u16 dest_wq;
+
+ DPAA_BUS_DEBUG("In shutdown for queue = %x", fqid);
+ p = get_affine_portal();
+ /* Determine the state of the FQID */
+ mcc = qm_mc_start(&p->p);
+ mcc->queryfq_np.fqid = cpu_to_be32(fqid);
+ qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ_NP);
+ if (!qm_mc_result_timeout(&p->p, &mcr)) {
+ DPAA_BUS_ERR("QUERYFQ_NP timeout");
+ ret = -ETIMEDOUT;
+ goto out;
+ }
+ state = mcr->queryfq_np.state & QM_MCR_NP_STATE_MASK;
+ if (state == QM_MCR_NP_STATE_OOS) {
+ DPAA_BUS_ERR("Already in OOS");
+ goto out; /* Already OOS, no need to do anymore checks */
+ }
+
+ /* Query which channel the FQ is using */
+ mcc = qm_mc_start(&p->p);
+ mcc->queryfq.fqid = cpu_to_be32(fqid);
+ qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ);
+ if (!qm_mc_result_timeout(&p->p, &mcr)) {
+ DPAA_BUS_ERR("QUERYFQ timeout");
+ ret = -ETIMEDOUT;
+ goto out;
+ }
+
+ /* Need to store these since the MCR gets reused */
+ dest_wq = be16_to_cpu(mcr->queryfq.fqd.dest_wq);
+ channel = dest_wq & 0x7;
+ wq = dest_wq >> 3;
+
+ switch (state) {
+ case QM_MCR_NP_STATE_TEN_SCHED:
+ case QM_MCR_NP_STATE_TRU_SCHED:
+ case QM_MCR_NP_STATE_ACTIVE:
+ case QM_MCR_NP_STATE_PARKED:
+ DPAA_BUS_DEBUG("In shutdown state is %d", state);
+ orl_empty = 0;
+ mcc = qm_mc_start(&p->p);
+ mcc->alterfq.fqid = cpu_to_be32(fqid);
+ qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_RETIRE);
+ if (!qm_mc_result_timeout(&p->p, &mcr)) {
+ DPAA_BUS_ERR("ALTER_RETIRE timeout");
+ ret = -ETIMEDOUT;
+ goto out;
+ }
+ res = mcr->result; /* Make a copy as we reuse MCR below */
+
+ if (res == QM_MCR_RESULT_OK)
+ drain_mr_fqrni(&p->p);
+
+ if (res == QM_MCR_RESULT_PENDING) {
+ /*
+ * Need to wait for the FQRN in the message ring, which
+ * will only occur once the FQ has been drained. In
+ * order for the FQ to drain the portal needs to be set
+ * to dequeue from the channel the FQ is scheduled on
+ */
+ int found_fqrn = 0;
+
+ /* Flag that we need to drain FQ */
+ drain = 1;
+
+ __maybe_unused u16 dequeue_wq = 0;
+ if (channel >= qm_channel_pool1 &&
+ channel < (u16)(qm_channel_pool1 + 15)) {
+ /* Pool channel, enable the bit in the portal */
+ dequeue_wq = (channel -
+ qm_channel_pool1 + 1) << 4 | wq;
+ } else if (channel < qm_channel_pool1) {
+ /* Dedicated channel */
+ dequeue_wq = wq;
+ } else {
+ DPAA_BUS_ERR("Can't recover FQ 0x%x, ch: 0x%x",
+ fqid, channel);
+ ret = -EBUSY;
+ goto out;
+ }
+ /* Set the sdqcr to drain this channel */
+ if (channel < qm_channel_pool1)
+ qm_dqrr_sdqcr_set(&p->p,
+ QM_SDQCR_TYPE_ACTIVE |
+ QM_SDQCR_CHANNELS_DEDICATED);
+ else
+ qm_dqrr_sdqcr_set(&p->p,
+ QM_SDQCR_TYPE_ACTIVE |
+ QM_SDQCR_CHANNELS_POOL_CONV
+ (channel));
+ do {
+ /* Keep draining DQRR while checking the MR*/
+ qm_dqrr_drain_nomatch(&p->p);
+ /* Process message ring too */
+ found_fqrn = qm_mr_drain(&p->p,
+ FQRN);
+ cpu_relax();
+ } while (!found_fqrn);
+ /* Restore SDQCR */
+ qm_dqrr_sdqcr_set(&p->p,
+ p->sdqcr);
+ }
+ if (res != QM_MCR_RESULT_OK &&
+ res != QM_MCR_RESULT_PENDING) {
+ DPAA_BUS_ERR("retire_fq failed: FQ 0x%x, res=0x%x",
+ fqid, res);
+ ret = -EIO;
+ goto out;
+ }
+ if (!(mcr->alterfq.fqs & QM_MCR_FQS_ORLPRESENT)) {
+ /*
+ * ORL had no entries, no need to wait until the
+ * ERNs come in
+ */
+ orl_empty = 1;
+ }
+ /*
+ * Retirement succeeded, check to see if FQ needs
+ * to be drained
+ */
+ if (drain || mcr->alterfq.fqs & QM_MCR_FQS_NOTEMPTY) {
+ /* FQ is Not Empty, drain using volatile DQ commands */
+ do {
+ u32 vdqcr = fqid | QM_VDQCR_NUMFRAMES_SET(3);
+
+ qm_dqrr_vdqcr_set(&p->p, vdqcr);
+ /*
+ * Wait for a dequeue and process the dequeues,
+ * making sure to empty the ring completely
+ */
+ } while (!qm_dqrr_drain_wait(&p->p, fqid, FQ_EMPTY));
+ }
+ while (!orl_empty) {
+ /* Wait for the ORL to have been completely drained */
+ orl_empty = qm_mr_drain(&p->p, FQRL);
+ cpu_relax();
+ }
+ mcc = qm_mc_start(&p->p);
+ mcc->alterfq.fqid = cpu_to_be32(fqid);
+ qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_OOS);
+ if (!qm_mc_result_timeout(&p->p, &mcr)) {
+ DPAA_BUS_ERR("OOS Timeout");
+ ret = -ETIMEDOUT;
+ goto out;
+ }
+
+ if (mcr->result != QM_MCR_RESULT_OK) {
+ DPAA_BUS_ERR("OOS after drain fail: FQ 0x%x (0x%x)",
+ fqid, mcr->result);
+ ret = -EIO;
+ goto out;
+ }
+ break;
+
+ case QM_MCR_NP_STATE_RETIRED:
+ /* Send OOS Command */
+ mcc = qm_mc_start(&p->p);
+ mcc->alterfq.fqid = cpu_to_be32(fqid);
+ qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_OOS);
+ if (!qm_mc_result_timeout(&p->p, &mcr)) {
+ DPAA_BUS_ERR("In RTEIRED to OOS timeout");
+ ret = -ETIMEDOUT;
+ goto out;
+ }
+
+ if (mcr->result != QM_MCR_RESULT_OK) {
+ DPAA_BUS_ERR("OOS fail: FQ 0x%x (0x%x)",
+ fqid, mcr->result);
+ ret = -EIO;
+ goto out;
+ }
+ break;
+
+ case QM_MCR_NP_STATE_OOS:
+ /* Done */
+ break;
+
+ default:
+ ret = -EIO;
+ }
+
+out:
+ return ret;
+}
+
+RTE_EXPORT_INTERNAL_SYMBOL(qman_shutdown_fq)
int qman_shutdown_fq(u32 fqid)
{
struct qman_portal *p;
@@ -2683,8 +3010,10 @@ int qman_shutdown_fq(u32 fqid)
cpu_relax();
DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ_NP);
state = mcr->queryfq_np.state & QM_MCR_NP_STATE_MASK;
- if (state == QM_MCR_NP_STATE_OOS)
+ if (state == QM_MCR_NP_STATE_OOS) {
+ DPAA_BUS_ERR("Already in OOS state");
return 0; /* Already OOS, no need to do anymore checks */
+ }
/* Query which channel the FQ is using */
mcc = qm_mc_start(low_p);
@@ -2714,6 +3043,9 @@ int qman_shutdown_fq(u32 fqid)
QM_MCR_VERB_ALTER_RETIRE);
result = mcr->result; /* Make a copy as we reuse MCR below */
+ if (result == QM_MCR_RESULT_OK)
+ drain_mr_fqrni(low_p);
+
if (result == QM_MCR_RESULT_PENDING) {
/* Need to wait for the FQRN in the message ring, which
* will only occur once the FQ has been drained. In
@@ -2737,7 +3069,7 @@ int qman_shutdown_fq(u32 fqid)
/* Dedicated channel */
dequeue_wq = wq;
} else {
- pr_info("Cannot recover FQ 0x%x,"
+ DPAA_BUS_ERR("Cannot recover FQ 0x%x,"
" it is scheduled on channel 0x%x",
fqid, channel);
return -EBUSY;
@@ -2782,8 +3114,8 @@ int qman_shutdown_fq(u32 fqid)
if (result != QM_MCR_RESULT_OK &&
result != QM_MCR_RESULT_PENDING) {
/* error */
- pr_err("qman_retire_fq failed on FQ 0x%x,"
- " result=0x%x\n", fqid, result);
+ DPAA_BUS_ERR("qman_retire_fq failed on FQ 0x%x, result=0x%x",
+ fqid, result);
return -1;
}
if (!(mcr->alterfq.fqs & QM_MCR_FQS_ORLPRESENT)) {
@@ -2853,8 +3185,8 @@ int qman_shutdown_fq(u32 fqid)
DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) ==
QM_MCR_VERB_ALTER_OOS);
if (mcr->result != QM_MCR_RESULT_OK) {
- pr_err(
- "OOS after drain Failed on FQID 0x%x, result 0x%x\n",
+ DPAA_BUS_ERR(
+ "OOS after drain Failed on FQID 0x%x, result 0x%x",
fqid, mcr->result);
return -1;
}
@@ -2869,8 +3201,8 @@ int qman_shutdown_fq(u32 fqid)
cpu_relax();
DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) ==
QM_MCR_VERB_ALTER_OOS);
- if (mcr->result) {
- pr_err("OOS Failed on FQID 0x%x\n", fqid);
+ if (mcr->result != QM_MCR_RESULT_OK) {
+ DPAA_BUS_ERR("OOS Failed on FQID 0x%x", fqid);
return -1;
}
return 0;
diff --git a/drivers/bus/dpaa/include/fsl_qman.h b/drivers/bus/dpaa/include/fsl_qman.h
index 71d5b16878..5b6015a876 100644
--- a/drivers/bus/dpaa/include/fsl_qman.h
+++ b/drivers/bus/dpaa/include/fsl_qman.h
@@ -1894,7 +1894,10 @@ static inline void qman_release_fqid(u32 fqid)
void qman_seed_fqid_range(u32 fqid, unsigned int count);
+__rte_internal
int qman_shutdown_fq(u32 fqid);
+__rte_internal
+int qman_shutdown_fq_new(u32 fqid);
/**
* qman_reserve_fqid_range - Reserve the specified range of frame queue IDs
diff --git a/drivers/net/dpaa/dpaa_ethdev.c b/drivers/net/dpaa/dpaa_ethdev.c
index 34b691fde7..30a0c97a8b 100644
--- a/drivers/net/dpaa/dpaa_ethdev.c
+++ b/drivers/net/dpaa/dpaa_ethdev.c
@@ -1134,6 +1134,9 @@ int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)",
queue_idx, rxq->fqid);
+ /* Shutdown FQ before configure */
+ qman_shutdown_fq(rxq->fqid);
+
if (!fif->num_profiles) {
if (dpaa_intf->bp_info && dpaa_intf->bp_info->bp &&
dpaa_intf->bp_info->mp != mp) {
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 2/5] net/dpaa: Support IEEE1588 by timesync API
2025-10-08 4:35 ` [PATCH v2 0/5] DPAA specific changes Gagandeep Singh
2025-10-08 4:35 ` [PATCH v2 1/5] bus/dpaa: add FQ shutdown and improve logging Gagandeep Singh
@ 2025-10-08 4:35 ` Gagandeep Singh
2025-10-08 4:35 ` [PATCH v2 3/5] bus/dpaa: Disable qman Invalid Enqueue State interrupt Gagandeep Singh
` (2 subsequent siblings)
4 siblings, 0 replies; 12+ messages in thread
From: Gagandeep Singh @ 2025-10-08 4:35 UTC (permalink / raw)
To: dev, Hemant Agrawal, Sachin Saxena; +Cc: Jun Yang
From: Jun Yang <jun.yang@nxp.com>
Enable IEEE1588 by timesync API instead of devargs.
DPAA1 HW parser has no capability to identify ptp packets
from ingress traffic, remove ptp identification code from
driver RX callback which impacts performance significantly.
Signed-off-by: Jun Yang <jun.yang@nxp.com>
---
doc/guides/nics/dpaa.rst | 3 -
drivers/bus/dpaa/base/qbman/qman.c | 18 +++---
drivers/bus/dpaa/include/fsl_qman.h | 5 +-
drivers/common/dpaax/dpaax_ptp.h | 95 +++++++++++++++++++++++++++++
drivers/net/dpaa/dpaa_ethdev.c | 15 ++---
drivers/net/dpaa/dpaa_ethdev.h | 13 ++--
drivers/net/dpaa/dpaa_ptp.c | 50 ++++++++++++---
drivers/net/dpaa/dpaa_rxtx.c | 93 +++++++++++++---------------
drivers/net/dpaa/dpaa_rxtx.h | 2 +-
9 files changed, 204 insertions(+), 90 deletions(-)
create mode 100644 drivers/common/dpaax/dpaax_ptp.h
diff --git a/doc/guides/nics/dpaa.rst b/doc/guides/nics/dpaa.rst
index 8cd57b21f3..8ffe31ce32 100644
--- a/doc/guides/nics/dpaa.rst
+++ b/doc/guides/nics/dpaa.rst
@@ -275,9 +275,6 @@ for details.
Done
testpmd>
-* Use dev arg option ``drv_ieee1588=1`` to enable IEEE 1588 support
- at driver level, e.g. ``dpaa:fm1-mac3,drv_ieee1588=1``.
-
* Use dev arg option ``recv_err_pkts=1`` to receive all packets including error packets
and thus disabling hardware based packet handling at driver level,
e.g. ``dpaa:fm1-mac3,recv_err_pkts=1``.
diff --git a/drivers/bus/dpaa/base/qbman/qman.c b/drivers/bus/dpaa/base/qbman/qman.c
index 6ce3690366..ec1fdb7cd3 100644
--- a/drivers/bus/dpaa/base/qbman/qman.c
+++ b/drivers/bus/dpaa/base/qbman/qman.c
@@ -1234,14 +1234,14 @@ u16 qman_affine_channel(int cpu)
return affine_channels[cpu];
}
-unsigned int qman_portal_poll_rx(unsigned int poll_limit,
- void **bufs,
- struct qman_portal *p)
+uint32_t
+qman_portal_poll_rx(uint32_t poll_limit, void **bufs,
+ struct qman_portal *p, struct qman_fq_cb *cb)
{
struct qm_portal *portal = &p->p;
register struct qm_dqrr *dqrr = &portal->dqrr;
struct qm_dqrr_entry *dq[QM_DQRR_SIZE], *shadow[QM_DQRR_SIZE];
- struct qman_fq *fq;
+ struct qman_fq *fq[QM_DQRR_SIZE];
unsigned int limit = 0, rx_number = 0;
uint32_t consume = 0;
@@ -1275,12 +1275,12 @@ unsigned int qman_portal_poll_rx(unsigned int poll_limit,
/* SDQCR: context_b points to the FQ */
#ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
- fq = qman_fq_lookup_table[dq[rx_number]->contextB];
+ fq[rx_number] = qman_fq_lookup_table[dq[rx_number]->contextB];
#else
- fq = (void *)dq[rx_number]->contextB;
+ fq[rx_number] = (void *)dq[rx_number]->contextB;
#endif
- if (fq->cb.dqrr_prepare)
- fq->cb.dqrr_prepare(shadow[rx_number],
+ if (fq[rx_number]->cb.dqrr_prepare)
+ fq[rx_number]->cb.dqrr_prepare(shadow[rx_number],
&bufs[rx_number]);
consume |= (1 << (31 - DQRR_PTR2IDX(shadow[rx_number])));
@@ -1289,7 +1289,7 @@ unsigned int qman_portal_poll_rx(unsigned int poll_limit,
} while (++limit < poll_limit);
if (rx_number)
- fq->cb.dqrr_dpdk_pull_cb(&fq, shadow, bufs, rx_number);
+ cb->dqrr_dpdk_pull_cb(fq, shadow, bufs, rx_number);
/* Consume all the DQRR enries together */
qm_out(DQRR_DCAP, (1 << 8) | consume);
diff --git a/drivers/bus/dpaa/include/fsl_qman.h b/drivers/bus/dpaa/include/fsl_qman.h
index 5b6015a876..93611cc234 100644
--- a/drivers/bus/dpaa/include/fsl_qman.h
+++ b/drivers/bus/dpaa/include/fsl_qman.h
@@ -1393,8 +1393,9 @@ int qman_fq_portal_irqsource_remove(struct qman_portal *p, u32 bits);
u16 qman_affine_channel(int cpu);
__rte_internal
-unsigned int qman_portal_poll_rx(unsigned int poll_limit,
- void **bufs, struct qman_portal *q);
+uint32_t
+qman_portal_poll_rx(uint32_t poll_limit, void **bufs,
+ struct qman_portal *p, struct qman_fq_cb *cb);
/**
* qman_set_vdq - Issue a volatile dequeue command
diff --git a/drivers/common/dpaax/dpaax_ptp.h b/drivers/common/dpaax/dpaax_ptp.h
new file mode 100644
index 0000000000..b73c16c986
--- /dev/null
+++ b/drivers/common/dpaax/dpaax_ptp.h
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright 2025 NXP
+ */
+
+#ifndef _DPAAX_PTP_H_
+#define _DPAAX_PTP_H_
+#include <stdlib.h>
+#include <rte_ether.h>
+#include <rte_ip.h>
+#include <rte_udp.h>
+
+#define UDP_PTP_EVENT_DST_PORT 319
+#define UDP_PTP_GENERAL_DST_PORT 320
+
+struct __rte_packed_begin rte_dpaax_ptp_header {
+ uint8_t tsmt; /* transportSpecific | messageType */
+ uint8_t ver; /* reserved | versionPTP */
+ rte_be16_t msg_len;
+ uint8_t domain_number;
+ uint8_t rsv;
+ uint8_t flags[2];
+ rte_be64_t correction;
+ uint8_t unused[];
+} __rte_packed_end;
+
+static inline struct rte_dpaax_ptp_header *
+dpaax_timesync_ptp_parse_header(struct rte_mbuf *buf,
+ uint16_t *ts_offset, int *is_udp)
+{
+ struct rte_ether_hdr *eth = rte_pktmbuf_mtod(buf, void *);
+ void *next_hdr;
+ rte_be16_t ether_type;
+ struct rte_vlan_hdr *vlan;
+ struct rte_ipv4_hdr *ipv4;
+ struct rte_ipv6_hdr *ipv6;
+ struct rte_udp_hdr *udp;
+ struct rte_dpaax_ptp_header *ptp = NULL;
+ uint16_t offset = offsetof(struct rte_dpaax_ptp_header, correction);
+
+ if (is_udp)
+ *is_udp = false;
+
+ offset += sizeof(struct rte_ether_hdr);
+ if (eth->ether_type == htons(RTE_ETHER_TYPE_1588)) {
+ ptp = (void *)(eth + 1);
+ goto quit;
+ }
+
+ if (eth->ether_type == htons(RTE_ETHER_TYPE_VLAN)) {
+ vlan = (void *)(eth + 1);
+ ether_type = vlan->eth_proto;
+ next_hdr = (void *)(vlan + 1);
+ offset += sizeof(struct rte_vlan_hdr);
+ if (ether_type == htons(RTE_ETHER_TYPE_1588)) {
+ ptp = next_hdr;
+ goto quit;
+ }
+ } else {
+ ether_type = eth->ether_type;
+ next_hdr = (void *)(eth + 1);
+ }
+
+ if (ether_type == htons(RTE_ETHER_TYPE_IPV4)) {
+ ipv4 = next_hdr;
+ offset += sizeof(struct rte_ipv4_hdr);
+ if (ipv4->next_proto_id != IPPROTO_UDP)
+ return NULL;
+ udp = (void *)(ipv4 + 1);
+ goto parse_udp;
+ } else if (ether_type == htons(RTE_ETHER_TYPE_IPV6)) {
+ ipv6 = next_hdr;
+ offset += sizeof(struct rte_ipv6_hdr);
+ if (ipv6->proto != IPPROTO_UDP)
+ return NULL;
+ udp = (void *)(ipv6 + 1);
+ goto parse_udp;
+ } else {
+ return NULL;
+ }
+parse_udp:
+ offset += sizeof(struct rte_udp_hdr);
+ if (udp->dst_port != UDP_PTP_EVENT_DST_PORT &&
+ udp->dst_port != UDP_PTP_GENERAL_DST_PORT)
+ return NULL;
+ ptp = (void *)(udp + 1);
+ if (is_udp)
+ *is_udp = true;
+quit:
+ if (ts_offset)
+ *ts_offset = offset;
+
+ return ptp;
+}
+
+#endif /* _DPAAX_PTP_H_ */
diff --git a/drivers/net/dpaa/dpaa_ethdev.c b/drivers/net/dpaa/dpaa_ethdev.c
index 30a0c97a8b..43aab98339 100644
--- a/drivers/net/dpaa/dpaa_ethdev.c
+++ b/drivers/net/dpaa/dpaa_ethdev.c
@@ -52,7 +52,6 @@
#include <process.h>
#include <fmlib/fm_ext.h>
-#define DRIVER_IEEE1588 "drv_ieee1588"
#define CHECK_INTERVAL 100 /* 100ms */
#define MAX_REPEAT_TIME 90 /* 9s (90 * 100ms) in total */
#define DRIVER_RECV_ERR_PKTS "recv_err_pkts"
@@ -88,7 +87,6 @@ static uint64_t dev_tx_offloads_nodis =
static int is_global_init;
static int fmc_q = 1; /* Indicates the use of static fmc for distribution */
static int default_q; /* use default queue - FMC is not executed*/
-int dpaa_ieee_1588; /* use to indicate if IEEE 1588 is enabled for the driver */
bool dpaa_enable_recv_err_pkts; /* Enable main queue to receive error packets */
/* At present we only allow up to 4 push mode queues as default - as each of
@@ -1998,6 +1996,7 @@ static int dpaa_tx_queue_init(struct qman_fq *fq,
}
};
int ret;
+ struct dpaa_if *dpaa_intf = fq->dpaa_intf;
ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
QMAN_FQ_FLAG_TO_DCPORTAL, fq);
@@ -2011,7 +2010,7 @@ static int dpaa_tx_queue_init(struct qman_fq *fq,
opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY;
opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE;
opts.fqd.context_b = 0;
- if (dpaa_ieee_1588) {
+ if (dpaa_intf->ts_enable) {
opts.fqd.context_a.lo = 0;
opts.fqd.context_a.hi =
fman_intf->fman->dealloc_bufs_mask_hi;
@@ -2063,7 +2062,7 @@ static int dpaa_tx_queue_init(struct qman_fq *fq,
return ret;
}
-static int
+int
dpaa_tx_conf_queue_init(struct qman_fq *fq)
{
struct qm_mcc_initfq opts = {0};
@@ -2261,9 +2260,6 @@ dpaa_dev_init(struct rte_eth_dev *eth_dev)
dpaa_intf->ifid = dev_id;
dpaa_intf->cfg = cfg;
- if (dpaa_get_devargs(dev->devargs, DRIVER_IEEE1588))
- dpaa_ieee_1588 = 1;
-
if (dpaa_get_devargs(dev->devargs, DRIVER_RECV_ERR_PKTS))
dpaa_enable_recv_err_pkts = 1;
@@ -2432,14 +2428,14 @@ dpaa_dev_init(struct rte_eth_dev *eth_dev)
if (dpaa_intf->cgr_tx)
dpaa_intf->cgr_tx[loop].cgrid = cgrid_tx[loop];
+ dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop],
fman_intf,
dpaa_intf->cgr_tx ? &dpaa_intf->cgr_tx[loop] : NULL);
if (ret)
goto free_tx;
- dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
- if (dpaa_ieee_1588) {
+ if (dpaa_intf->ts_enable) {
ret = dpaa_tx_conf_queue_init(&dpaa_intf->tx_conf_queues[loop]);
if (ret)
goto free_tx;
@@ -2731,6 +2727,5 @@ static struct rte_dpaa_driver rte_dpaa_pmd = {
RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd);
RTE_PMD_REGISTER_PARAM_STRING(net_dpaa,
- DRIVER_IEEE1588 "=<int>"
DRIVER_RECV_ERR_PKTS "=<int>");
RTE_LOG_REGISTER_DEFAULT(dpaa_logtype_pmd, NOTICE);
diff --git a/drivers/net/dpaa/dpaa_ethdev.h b/drivers/net/dpaa/dpaa_ethdev.h
index be9398004f..f400030a5c 100644
--- a/drivers/net/dpaa/dpaa_ethdev.h
+++ b/drivers/net/dpaa/dpaa_ethdev.h
@@ -119,7 +119,6 @@ enum {
#define FMC_FILE "/tmp/fmc.bin"
extern struct rte_mempool *dpaa_tx_sg_pool;
-extern int dpaa_ieee_1588;
/* PMD related logs */
extern int dpaa_logtype_pmd;
@@ -154,10 +153,12 @@ struct dpaa_if {
void *netenv_handle;
void *scheme_handle[2];
uint32_t scheme_count;
+ int ts_enable;
/*stores timestamp of last received packet on dev*/
uint64_t rx_timestamp;
/*stores timestamp of last received tx confirmation packet on dev*/
uint64_t tx_timestamp;
+ uint64_t tx_old_timestamp;
/* stores pointer to next tx_conf queue that should be processed,
* it corresponds to last packet transmitted
*/
@@ -244,6 +245,9 @@ struct dpaa_if_rx_bmi_stats {
uint32_t fmbm_rbdc; /**< Rx Buffers Deallocate Counter*/
};
+int
+dpaa_tx_conf_queue_init(struct qman_fq *fq);
+
int
dpaa_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
struct timespec *timestamp);
@@ -256,18 +260,17 @@ dpaa_timesync_disable(struct rte_eth_dev *dev);
int
dpaa_timesync_read_time(struct rte_eth_dev *dev,
- struct timespec *timestamp);
+ struct timespec *timestamp);
int
dpaa_timesync_write_time(struct rte_eth_dev *dev,
- const struct timespec *timestamp);
+ const struct timespec *timestamp);
int
dpaa_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
int
dpaa_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
- struct timespec *timestamp,
- uint32_t flags __rte_unused);
+ struct timespec *timestamp, uint32_t flags __rte_unused);
uint8_t
fm_default_vsp_id(struct fman_if *fif);
diff --git a/drivers/net/dpaa/dpaa_ptp.c b/drivers/net/dpaa/dpaa_ptp.c
index 8482666745..e9b332c571 100644
--- a/drivers/net/dpaa/dpaa_ptp.c
+++ b/drivers/net/dpaa/dpaa_ptp.c
@@ -17,20 +17,40 @@
#include <dpaa_rxtx.h>
int
-dpaa_timesync_enable(struct rte_eth_dev *dev __rte_unused)
+dpaa_timesync_enable(struct rte_eth_dev *dev)
{
+ struct dpaa_if *dpaa_intf = dev->data->dev_private;
+ int loop, ret = 0;
+
+ for (loop = 0; loop < MAX_DPAA_CORES; loop++) {
+ if (!dpaa_intf->tx_queues[loop].tx_conf_queue) {
+ ret = dpaa_tx_conf_queue_init(&dpaa_intf->tx_conf_queues[loop]);
+ if (ret)
+ break;
+ dpaa_intf->tx_conf_queues[loop].dpaa_intf = dpaa_intf;
+ dpaa_intf->tx_queues[loop].tx_conf_queue = &dpaa_intf->tx_conf_queues[loop];
+ }
+ }
+
+ if (ret)
+ return ret;
+
+ dpaa_intf->ts_enable = true;
return 0;
}
int
-dpaa_timesync_disable(struct rte_eth_dev *dev __rte_unused)
+dpaa_timesync_disable(struct rte_eth_dev *dev)
{
+ struct dpaa_if *dpaa_intf = dev->data->dev_private;
+
+ dpaa_intf->ts_enable = false;
return 0;
}
int
dpaa_timesync_read_time(struct rte_eth_dev *dev,
- struct timespec *timestamp)
+ struct timespec *timestamp)
{
uint32_t *tmr_cnt_h, *tmr_cnt_l;
struct fman_if *fif;
@@ -50,7 +70,7 @@ dpaa_timesync_read_time(struct rte_eth_dev *dev,
int
dpaa_timesync_write_time(struct rte_eth_dev *dev,
- const struct timespec *ts)
+ const struct timespec *ts)
{
uint32_t *tmr_cnt_h, *tmr_cnt_l;
struct fman_if *fif;
@@ -88,15 +108,21 @@ dpaa_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
int
dpaa_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
- struct timespec *timestamp)
+ struct timespec *timestamp)
{
struct dpaa_if *dpaa_intf = dev->data->dev_private;
+ int read_count = 10000;
- if (dpaa_intf->next_tx_conf_queue) {
- while (!dpaa_intf->tx_timestamp)
+ if (dpaa_intf->ts_enable && dpaa_intf->next_tx_conf_queue) {
+ while (dpaa_intf->tx_timestamp == dpaa_intf->tx_old_timestamp) {
dpaa_eth_tx_conf(dpaa_intf->next_tx_conf_queue);
+ if (read_count <= 0)
+ return -EAGAIN;
+ read_count--;
+ }
+ dpaa_intf->tx_old_timestamp = dpaa_intf->tx_timestamp;
} else {
- return -1;
+ return -ENOTSUP;
}
*timestamp = rte_ns_to_timespec(dpaa_intf->tx_timestamp);
@@ -105,10 +131,14 @@ dpaa_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
int
dpaa_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
- struct timespec *timestamp,
- uint32_t flags __rte_unused)
+ struct timespec *timestamp, uint32_t flags __rte_unused)
{
struct dpaa_if *dpaa_intf = dev->data->dev_private;
+
+ if (!dpaa_intf->ts_enable)
+ return -ENOTSUP;
+
*timestamp = rte_ns_to_timespec(dpaa_intf->rx_timestamp);
+
return 0;
}
diff --git a/drivers/net/dpaa/dpaa_rxtx.c b/drivers/net/dpaa/dpaa_rxtx.c
index 4dca63ea7e..c5e393159a 100644
--- a/drivers/net/dpaa/dpaa_rxtx.c
+++ b/drivers/net/dpaa/dpaa_rxtx.c
@@ -45,6 +45,7 @@
#include <fsl_qman.h>
#include <fsl_bman.h>
#include <dpaa_of.h>
+#include <dpaax_ptp.h>
#include <netcfg.h>
#ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
@@ -234,12 +235,11 @@ dpaa_slow_parsing(struct rte_mbuf *m,
m->packet_type |= RTE_PTYPE_L4_SCTP;
}
-static inline void dpaa_eth_packet_info(struct rte_mbuf *m, void *fd_virt_addr)
+static inline void
+dpaa_eth_packet_info(struct dpaa_if *dpaa_intf, struct rte_mbuf *m,
+ struct annotations_t *annot)
{
- struct annotations_t *annot = GET_ANNOTATIONS(fd_virt_addr);
uint64_t prs = *((uintptr_t *)(&annot->parse)) & DPAA_PARSE_MASK;
- struct rte_ether_hdr *eth_hdr =
- rte_pktmbuf_mtod(m, struct rte_ether_hdr *);
DPAA_DP_LOG(DEBUG, " Parsing mbuf: %p with annotations: %p", m, annot);
@@ -360,9 +360,11 @@ static inline void dpaa_eth_packet_info(struct rte_mbuf *m, void *fd_virt_addr)
m->ol_flags |= RTE_MBUF_F_RX_VLAN;
/* Packet received without stripping the vlan */
- if (eth_hdr->ether_type == htons(RTE_ETHER_TYPE_1588)) {
- m->ol_flags |= RTE_MBUF_F_RX_IEEE1588_PTP;
- m->ol_flags |= RTE_MBUF_F_RX_IEEE1588_TMST;
+ if (unlikely(dpaa_intf->ts_enable)) {
+ if (dpaax_timesync_ptp_parse_header(m, NULL, NULL)) {
+ m->ol_flags |= RTE_MBUF_F_RX_IEEE1588_PTP;
+ m->ol_flags |= RTE_MBUF_F_RX_IEEE1588_TMST;
+ }
}
}
@@ -468,7 +470,7 @@ dpaa_unsegmented_checksum(struct rte_mbuf *mbuf, struct qm_fd *fd_arr)
}
static struct rte_mbuf *
-dpaa_eth_sg_to_mbuf(const struct qm_fd *fd, uint32_t ifid)
+dpaa_eth_sg_to_mbuf(struct dpaa_if *dpaa_intf, const struct qm_fd *fd)
{
struct dpaa_bp_info *bp_info = DPAA_BPID_TO_POOL_INFO(fd->bpid);
struct rte_mbuf *first_seg, *prev_seg, *cur_seg, *temp;
@@ -499,7 +501,7 @@ dpaa_eth_sg_to_mbuf(const struct qm_fd *fd, uint32_t ifid)
(void **)&first_seg, 1, 1);
#endif
- first_seg->port = ifid;
+ first_seg->port = dpaa_intf->ifid;
first_seg->nb_segs = 1;
first_seg->ol_flags = 0;
prev_seg = first_seg;
@@ -529,7 +531,7 @@ dpaa_eth_sg_to_mbuf(const struct qm_fd *fd, uint32_t ifid)
DPAA_DP_LOG(DEBUG, "Received an SG frame len =%d, num_sg =%d",
first_seg->pkt_len, first_seg->nb_segs);
- dpaa_eth_packet_info(first_seg, vaddr);
+ dpaa_eth_packet_info(dpaa_intf, first_seg, GET_ANNOTATIONS(vaddr));
#ifdef RTE_LIBRTE_MEMPOOL_DEBUG
rte_mempool_check_cookies(rte_mempool_from_obj((void *)temp),
(void **)&temp, 1, 1);
@@ -540,7 +542,7 @@ dpaa_eth_sg_to_mbuf(const struct qm_fd *fd, uint32_t ifid)
}
static inline struct rte_mbuf *
-dpaa_eth_fd_to_mbuf(const struct qm_fd *fd, uint32_t ifid)
+dpaa_eth_fd_to_mbuf(struct dpaa_if *dpaa_intf, const struct qm_fd *fd)
{
struct rte_mbuf *mbuf;
struct dpaa_bp_info *bp_info = DPAA_BPID_TO_POOL_INFO(fd->bpid);
@@ -551,7 +553,7 @@ dpaa_eth_fd_to_mbuf(const struct qm_fd *fd, uint32_t ifid)
uint32_t length;
if (unlikely(format == qm_fd_sg))
- return dpaa_eth_sg_to_mbuf(fd, ifid);
+ return dpaa_eth_sg_to_mbuf(dpaa_intf, fd);
offset = (fd->opaque & DPAA_FD_OFFSET_MASK) >> DPAA_FD_OFFSET_SHIFT;
length = fd->opaque & DPAA_FD_LENGTH_MASK;
@@ -569,7 +571,7 @@ dpaa_eth_fd_to_mbuf(const struct qm_fd *fd, uint32_t ifid)
mbuf->data_len = length;
mbuf->pkt_len = length;
- mbuf->port = ifid;
+ mbuf->port = dpaa_intf->ifid;
mbuf->nb_segs = 1;
mbuf->ol_flags = 0;
mbuf->next = NULL;
@@ -578,7 +580,7 @@ dpaa_eth_fd_to_mbuf(const struct qm_fd *fd, uint32_t ifid)
rte_mempool_check_cookies(rte_mempool_from_obj((void *)mbuf),
(void **)&mbuf, 1, 1);
#endif
- dpaa_eth_packet_info(mbuf, mbuf->buf_addr);
+ dpaa_eth_packet_info(dpaa_intf, mbuf, GET_ANNOTATIONS(mbuf->buf_addr));
return mbuf;
}
@@ -670,11 +672,11 @@ dpaa_rx_cb_no_prefetch(struct qman_fq **fq, struct qm_dqrr_entry **dqrr,
}
fd = &dqrr[i]->fd;
- dpaa_intf = fq[0]->dpaa_intf;
+ dpaa_intf = fq[i]->dpaa_intf;
format = (fd->opaque & DPAA_FD_FORMAT_MASK) >>
DPAA_FD_FORMAT_SHIFT;
if (unlikely(format == qm_fd_sg)) {
- bufs[i] = dpaa_eth_sg_to_mbuf(fd, dpaa_intf->ifid);
+ bufs[i] = dpaa_eth_sg_to_mbuf(dpaa_intf, fd);
continue;
}
@@ -696,13 +698,11 @@ dpaa_rx_cb_no_prefetch(struct qman_fq **fq, struct qm_dqrr_entry **dqrr,
rte_mempool_check_cookies(rte_mempool_from_obj((void *)mbuf),
(void **)&mbuf, 1, 1);
#endif
- dpaa_eth_packet_info(mbuf, mbuf->buf_addr);
- dpaa_display_frame_info(fd, fq[0]->fqid, true);
- if (dpaa_ieee_1588) {
- annot = GET_ANNOTATIONS(mbuf->buf_addr);
- dpaa_intf->rx_timestamp =
- rte_cpu_to_be_64(annot->timestamp);
- }
+ annot = GET_ANNOTATIONS(mbuf->buf_addr);
+ dpaa_eth_packet_info(dpaa_intf, mbuf, annot);
+ dpaa_display_frame_info(fd, fq[i]->fqid, true);
+ if (unlikely(dpaa_intf->ts_enable))
+ dpaa_intf->rx_timestamp = rte_be_to_cpu_64(annot->timestamp);
}
}
@@ -720,11 +720,11 @@ dpaa_rx_cb(struct qman_fq **fq, struct qm_dqrr_entry **dqrr,
for (i = 0; i < num_bufs; i++) {
fd = &dqrr[i]->fd;
- dpaa_intf = fq[0]->dpaa_intf;
+ dpaa_intf = fq[i]->dpaa_intf;
format = (fd->opaque & DPAA_FD_FORMAT_MASK) >>
DPAA_FD_FORMAT_SHIFT;
if (unlikely(format == qm_fd_sg)) {
- bufs[i] = dpaa_eth_sg_to_mbuf(fd, dpaa_intf->ifid);
+ bufs[i] = dpaa_eth_sg_to_mbuf(dpaa_intf, fd);
continue;
}
@@ -746,13 +746,11 @@ dpaa_rx_cb(struct qman_fq **fq, struct qm_dqrr_entry **dqrr,
rte_mempool_check_cookies(rte_mempool_from_obj((void *)mbuf),
(void **)&mbuf, 1, 1);
#endif
- dpaa_eth_packet_info(mbuf, mbuf->buf_addr);
- dpaa_display_frame_info(fd, fq[0]->fqid, true);
- if (dpaa_ieee_1588) {
- annot = GET_ANNOTATIONS(mbuf->buf_addr);
- dpaa_intf->rx_timestamp =
- rte_cpu_to_be_64(annot->timestamp);
- }
+ annot = GET_ANNOTATIONS(mbuf->buf_addr);
+ dpaa_eth_packet_info(dpaa_intf, mbuf, annot);
+ dpaa_display_frame_info(fd, fq[i]->fqid, true);
+ if (unlikely(dpaa_intf->ts_enable))
+ dpaa_intf->rx_timestamp = rte_be_to_cpu_64(annot->timestamp);
}
}
@@ -787,7 +785,7 @@ dpaa_eth_queue_portal_rx(struct qman_fq *fq,
fq->qp_initialized = 1;
}
- return qman_portal_poll_rx(nb_bufs, (void **)bufs, fq->qp);
+ return qman_portal_poll_rx(nb_bufs, (void **)bufs, fq->qp, &fq->cb);
}
enum qman_cb_dqrr_result
@@ -797,11 +795,10 @@ dpaa_rx_cb_parallel(void *event,
const struct qm_dqrr_entry *dqrr,
void **bufs)
{
- u32 ifid = ((struct dpaa_if *)fq->dpaa_intf)->ifid;
struct rte_mbuf *mbuf;
struct rte_event *ev = (struct rte_event *)event;
- mbuf = dpaa_eth_fd_to_mbuf(&dqrr->fd, ifid);
+ mbuf = dpaa_eth_fd_to_mbuf(fq->dpaa_intf, &dqrr->fd);
ev->event_ptr = (void *)mbuf;
ev->flow_id = fq->ev.flow_id;
ev->sub_event_type = fq->ev.sub_event_type;
@@ -825,11 +822,10 @@ dpaa_rx_cb_atomic(void *event,
void **bufs)
{
u8 index;
- u32 ifid = ((struct dpaa_if *)fq->dpaa_intf)->ifid;
struct rte_mbuf *mbuf;
struct rte_event *ev = (struct rte_event *)event;
- mbuf = dpaa_eth_fd_to_mbuf(&dqrr->fd, ifid);
+ mbuf = dpaa_eth_fd_to_mbuf(fq->dpaa_intf, &dqrr->fd);
ev->event_ptr = (void *)mbuf;
ev->flow_id = fq->ev.flow_id;
ev->sub_event_type = fq->ev.sub_event_type;
@@ -900,7 +896,7 @@ dpaa_eth_err_queue(struct qman_fq *fq)
dpaa_display_frame_info(fd, debug_fq->fqid,
i == DPAA_DEBUG_FQ_RX_ERROR);
- mbuf = dpaa_eth_fd_to_mbuf(fd, dpaa_intf->ifid);
+ mbuf = dpaa_eth_fd_to_mbuf(dpaa_intf, fd);
rte_pktmbuf_free(mbuf);
qman_dqrr_consume(debug_fq, dq);
} while (debug_fq->flags & QMAN_FQ_STATE_VDQCR);
@@ -908,13 +904,12 @@ dpaa_eth_err_queue(struct qman_fq *fq)
}
#endif
-uint16_t dpaa_eth_queue_rx(void *q,
- struct rte_mbuf **bufs,
- uint16_t nb_bufs)
+uint16_t
+dpaa_eth_queue_rx(void *q, struct rte_mbuf **bufs, uint16_t nb_bufs)
{
struct qman_fq *fq = q;
struct qm_dqrr_entry *dq;
- uint32_t num_rx = 0, ifid = ((struct dpaa_if *)fq->dpaa_intf)->ifid;
+ uint32_t num_rx = 0;
int num_rx_bufs, ret;
uint32_t vdqcr_flags = 0;
struct annotations_t *annot;
@@ -959,11 +954,11 @@ uint16_t dpaa_eth_queue_rx(void *q,
dq = qman_dequeue(fq);
if (!dq)
continue;
- bufs[num_rx++] = dpaa_eth_fd_to_mbuf(&dq->fd, ifid);
+ bufs[num_rx++] = dpaa_eth_fd_to_mbuf(dpaa_intf, &dq->fd);
dpaa_display_frame_info(&dq->fd, fq->fqid, true);
- if (dpaa_ieee_1588) {
+ if (unlikely(dpaa_intf->ts_enable)) {
annot = GET_ANNOTATIONS(bufs[num_rx - 1]->buf_addr);
- dpaa_intf->rx_timestamp = rte_cpu_to_be_64(annot->timestamp);
+ dpaa_intf->rx_timestamp = rte_be_to_cpu_64(annot->timestamp);
}
qman_dqrr_consume(fq, dq);
} while (fq->flags & QMAN_FQ_STATE_VDQCR);
@@ -1314,10 +1309,9 @@ dpaa_eth_queue_tx(void *q, struct rte_mbuf **bufs, uint16_t nb_bufs)
DPAA_DP_LOG(DEBUG, "Transmitting %d buffers on queue: %p", nb_bufs, q);
- if (dpaa_ieee_1588) {
+ if (unlikely(dpaa_intf->ts_enable)) {
dpaa_intf->next_tx_conf_queue = fq_txconf;
dpaa_eth_tx_conf(fq_txconf);
- dpaa_intf->tx_timestamp = 0;
}
while (nb_bufs) {
@@ -1326,7 +1320,7 @@ dpaa_eth_queue_tx(void *q, struct rte_mbuf **bufs, uint16_t nb_bufs)
for (loop = 0; loop < frames_to_send; loop++) {
mbuf = *(bufs++);
fd_arr[loop].cmd = 0;
- if (dpaa_ieee_1588) {
+ if (unlikely(dpaa_intf->ts_enable)) {
fd_arr[loop].cmd |= DPAA_FD_CMD_FCO |
qman_fq_fqid(fq_txconf);
fd_arr[loop].cmd |= DPAA_FD_CMD_RPD |
@@ -1481,8 +1475,7 @@ dpaa_eth_tx_conf(void *q)
if (mbuf->ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST) {
annot = GET_ANNOTATIONS(mbuf->buf_addr);
- dpaa_intf->tx_timestamp =
- rte_cpu_to_be_64(annot->timestamp);
+ dpaa_intf->tx_timestamp = rte_be_to_cpu_64(annot->timestamp);
}
dpaa_display_frame_info(&dq->fd, fq->fqid, true);
qman_dqrr_consume(fq, dq);
diff --git a/drivers/net/dpaa/dpaa_rxtx.h b/drivers/net/dpaa/dpaa_rxtx.h
index edb29788fb..233339a488 100644
--- a/drivers/net/dpaa/dpaa_rxtx.h
+++ b/drivers/net/dpaa/dpaa_rxtx.h
@@ -239,7 +239,7 @@ struct __rte_packed_begin dpaa_eth_parse_results_t {
struct annotations_t {
uint8_t reserved[DEFAULT_RX_ICEOF];
struct dpaa_eth_parse_results_t parse; /**< Pointer to Parsed result*/
- uint64_t timestamp;
+ rte_be64_t timestamp;
uint64_t hash; /**< Hash Result */
};
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 3/5] bus/dpaa: Disable qman Invalid Enqueue State interrupt
2025-10-08 4:35 ` [PATCH v2 0/5] DPAA specific changes Gagandeep Singh
2025-10-08 4:35 ` [PATCH v2 1/5] bus/dpaa: add FQ shutdown and improve logging Gagandeep Singh
2025-10-08 4:35 ` [PATCH v2 2/5] net/dpaa: Support IEEE1588 by timesync API Gagandeep Singh
@ 2025-10-08 4:35 ` Gagandeep Singh
2025-10-08 4:35 ` [PATCH v2 4/5] bus/dpaa: Set max push RXQ number Gagandeep Singh
2025-10-08 4:35 ` [PATCH v2 5/5] net/dpaa: Fix coverity issue Gagandeep Singh
4 siblings, 0 replies; 12+ messages in thread
From: Gagandeep Singh @ 2025-10-08 4:35 UTC (permalink / raw)
To: dev, Hemant Agrawal, Sachin Saxena; +Cc: Jun Yang
From: Jun Yang <jun.yang@nxp.com>
ShareMAC port is still alive after dpdk process quits but RXQ setup
in dpdk process is in invalid state. If high loading ingress traffic
hits the FMan PCD then it's en-queued to the RXQ to generate frequent
interrupts. This causes system stuck.
User can disable this kind of interrupt by env to avoid this issue:
export DPAA_QMAN_IESR_ISR_DISABLE=1
Signed-off-by: Jun Yang <jun.yang@nxp.com>
---
drivers/bus/dpaa/base/qbman/qman_driver.c | 27 ++++++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/bus/dpaa/base/qbman/qman_driver.c b/drivers/bus/dpaa/base/qbman/qman_driver.c
index cdce6b777b..dc84260731 100644
--- a/drivers/bus/dpaa/base/qbman/qman_driver.c
+++ b/drivers/bus/dpaa/base/qbman/qman_driver.c
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
*
* Copyright 2008-2016 Freescale Semiconductor Inc.
- * Copyright 2017-2022 NXP
+ * Copyright 2017-2022, 2025 NXP
*
*/
@@ -32,6 +32,29 @@ static __thread struct dpaa_ioctl_portal_map map = {
.type = dpaa_portal_qman
};
+#define REG_ERR_IER 0x0e04
+#define QM_EIRQ_IESI 0x00000004
+
+static void dpaa_qm_iesr_irq_control(void)
+{
+ char *env = getenv("DPAA_QMAN_IESR_ISR_DISABLE");
+ uint32_t val;
+
+ if (!qman_ccsr_map) {
+ pr_err("qman CCSR not mapped!\n");
+ return;
+ }
+
+ val = in_be32((void *)((uintptr_t)qman_ccsr_map + REG_ERR_IER));
+
+ if (!env || atoi(env) == 0)
+ val = val | QM_EIRQ_IESI;
+ else
+ val = val & (~((uint32_t)QM_EIRQ_IESI));
+
+ out_be32((void *)((uintptr_t)qman_ccsr_map + REG_ERR_IER), val);
+}
+
u16 dpaa_get_qm_channel_caam(void)
{
return qm_channel_caam;
@@ -343,6 +366,8 @@ int qman_global_init(void)
return -EINVAL;
}
+ dpaa_qm_iesr_irq_control();
+
clk = of_get_property(dt_node, "clock-frequency", NULL);
if (!clk)
pr_warn("Can't find Qman clock frequency\n");
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 4/5] bus/dpaa: Set max push RXQ number
2025-10-08 4:35 ` [PATCH v2 0/5] DPAA specific changes Gagandeep Singh
` (2 preceding siblings ...)
2025-10-08 4:35 ` [PATCH v2 3/5] bus/dpaa: Disable qman Invalid Enqueue State interrupt Gagandeep Singh
@ 2025-10-08 4:35 ` Gagandeep Singh
2025-10-08 4:35 ` [PATCH v2 5/5] net/dpaa: Fix coverity issue Gagandeep Singh
4 siblings, 0 replies; 12+ messages in thread
From: Gagandeep Singh @ 2025-10-08 4:35 UTC (permalink / raw)
To: dev, Hemant Agrawal, Sachin Saxena; +Cc: Jun Yang
From: Jun Yang <jun.yang@nxp.com>
Max push queue number is bus level number affecting all dpaa devices.
Move the configuration from PMD driver to bus driver.
Signed-off-by: Jun Yang <jun.yang@nxp.com>
---
drivers/bus/dpaa/bus_dpaa_driver.h | 6 ++++
drivers/bus/dpaa/dpaa_bus.c | 51 ++++++++++++++++++++++++++++++
drivers/net/dpaa/dpaa_ethdev.c | 51 ++++++++----------------------
3 files changed, 70 insertions(+), 38 deletions(-)
diff --git a/drivers/bus/dpaa/bus_dpaa_driver.h b/drivers/bus/dpaa/bus_dpaa_driver.h
index 976f356699..cca0543432 100644
--- a/drivers/bus/dpaa/bus_dpaa_driver.h
+++ b/drivers/bus/dpaa/bus_dpaa_driver.h
@@ -249,6 +249,12 @@ struct fm_eth_port_cfg *dpaa_get_eth_port_cfg(int dev_id);
__rte_internal
uint32_t dpaa_soc_ver(void);
+__rte_internal
+int dpaa_push_queue_num_update(void);
+
+__rte_internal
+uint16_t dpaa_push_queue_max_num(void);
+
#ifdef __cplusplus
}
#endif
diff --git a/drivers/bus/dpaa/dpaa_bus.c b/drivers/bus/dpaa/dpaa_bus.c
index 1a35aa52df..d9830b68ca 100644
--- a/drivers/bus/dpaa/dpaa_bus.c
+++ b/drivers/bus/dpaa/dpaa_bus.c
@@ -50,6 +50,13 @@
#define DPAA_SVR_MASK 0xffff0000
#define RTE_PRIORITY_102 102
+#define DPAA_PUSH_RXQ_NUM_ARG "dpaa_push_rxq_num"
+/* At present we allow up to 4 push mode queues as default - as each of
+ * this queue need dedicated portal and we are short of portals.
+ */
+#define DPAA_MAX_PUSH_MODE_QUEUE 8
+#define DPAA_DEFAULT_PUSH_MODE_QUEUE 4
+
struct rte_dpaa_bus {
struct rte_bus bus;
TAILQ_HEAD(, rte_dpaa_device) device_list;
@@ -57,6 +64,8 @@ struct rte_dpaa_bus {
int device_count;
int detected;
uint32_t svr_ver;
+ uint16_t max_push_rxq_num;
+ RTE_ATOMIC(uint16_t) push_rxq_num;
};
static struct rte_dpaa_bus rte_dpaa_bus;
@@ -91,6 +100,34 @@ dpaa_get_eth_port_cfg(int dev_id)
return &dpaa_netcfg->port_cfg[dev_id];
}
+RTE_EXPORT_INTERNAL_SYMBOL(dpaa_push_queue_num_update)
+int
+dpaa_push_queue_num_update(void)
+{
+ int ret = false;
+ uint16_t current, new_val;
+
+ current = rte_atomic_load_explicit(&rte_dpaa_bus.push_rxq_num,
+ rte_memory_order_acquire);
+ if (current < rte_dpaa_bus.max_push_rxq_num) {
+ new_val = current + 1;
+ if (rte_atomic_compare_exchange_strong_explicit(&rte_dpaa_bus.push_rxq_num,
+ ¤t, new_val,
+ rte_memory_order_release,
+ rte_memory_order_acquire))
+ ret = true;
+ }
+
+ return ret;
+}
+
+RTE_EXPORT_INTERNAL_SYMBOL(dpaa_push_queue_max_num)
+uint16_t
+dpaa_push_queue_max_num(void)
+{
+ return rte_dpaa_bus.max_push_rxq_num;
+}
+
static int
compare_dpaa_devices(struct rte_dpaa_device *dev1,
struct rte_dpaa_device *dev2)
@@ -681,6 +718,7 @@ rte_dpaa_bus_probe(void)
uint32_t svr_ver;
int probe_all = rte_dpaa_bus.bus.conf.scan_mode != RTE_BUS_SCAN_ALLOWLIST;
static int process_once;
+ char *penv;
/* If DPAA bus is not present nothing needs to be done */
if (!rte_dpaa_bus.detected)
@@ -709,6 +747,18 @@ rte_dpaa_bus_probe(void)
rte_dpaa_bus.svr_ver);
}
+ /* Disabling the default push mode for LS1043A */
+ if (rte_dpaa_bus.svr_ver == SVR_LS1043A_FAMILY) {
+ rte_dpaa_bus.max_push_rxq_num = 0;
+ return 0;
+ }
+
+ penv = getenv("DPAA_PUSH_QUEUES_NUMBER");
+ if (penv)
+ rte_dpaa_bus.max_push_rxq_num = atoi(penv);
+ if (rte_dpaa_bus.max_push_rxq_num > DPAA_MAX_PUSH_MODE_QUEUE)
+ rte_dpaa_bus.max_push_rxq_num = DPAA_MAX_PUSH_MODE_QUEUE;
+
/* Device list creation is only done once */
if (!process_once) {
rte_dpaa_bus_dev_build();
@@ -947,6 +997,7 @@ static struct rte_dpaa_bus rte_dpaa_bus = {
.dev_iterate = dpaa_bus_dev_iterate,
.cleanup = dpaa_bus_cleanup,
},
+ .max_push_rxq_num = DPAA_DEFAULT_PUSH_MODE_QUEUE,
.device_list = TAILQ_HEAD_INITIALIZER(rte_dpaa_bus.device_list),
.driver_list = TAILQ_HEAD_INITIALIZER(rte_dpaa_bus.driver_list),
.device_count = 0,
diff --git a/drivers/net/dpaa/dpaa_ethdev.c b/drivers/net/dpaa/dpaa_ethdev.c
index 43aab98339..0baf5c03fa 100644
--- a/drivers/net/dpaa/dpaa_ethdev.c
+++ b/drivers/net/dpaa/dpaa_ethdev.c
@@ -89,16 +89,6 @@ static int fmc_q = 1; /* Indicates the use of static fmc for distribution */
static int default_q; /* use default queue - FMC is not executed*/
bool dpaa_enable_recv_err_pkts; /* Enable main queue to receive error packets */
-/* At present we only allow up to 4 push mode queues as default - as each of
- * this queue need dedicated portal and we are short of portals.
- */
-#define DPAA_MAX_PUSH_MODE_QUEUE 8
-#define DPAA_DEFAULT_PUSH_MODE_QUEUE 4
-
-static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE;
-static int dpaa_push_queue_idx; /* Queue index which are in push mode*/
-
-
/* Per RX FQ Taildrop in frame count */
static unsigned int td_threshold = CGR_RX_PERFQ_THRESH;
@@ -1113,7 +1103,7 @@ int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx];
struct qm_mcc_initfq opts = {0};
u32 ch_id, flags = 0;
- int ret;
+ int ret, set_push_rxq = false;
u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
uint32_t max_rx_pktlen;
@@ -1214,12 +1204,12 @@ int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name,
fman_if_get_sg_enable(fif), max_rx_pktlen);
/* checking if push mode only, no error check for now */
- if (!rxq->is_static &&
- dpaa_push_mode_max_queue > dpaa_push_queue_idx) {
+ if (!rxq->is_static)
+ set_push_rxq = dpaa_push_queue_num_update();
+ if (set_push_rxq) {
struct qman_portal *qp;
int q_fd;
- dpaa_push_queue_idx++;
opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK |
QM_FQCTRL_CTXASTASHING |
@@ -1269,7 +1259,7 @@ int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
qp = fsl_qman_fq_portal_create(&q_fd);
if (!qp) {
DPAA_PMD_ERR("Unable to alloc fq portal");
- return -1;
+ return -EIO;
}
rxq->qp = qp;
@@ -1279,19 +1269,19 @@ int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
struct rte_device *rdev = dev->device;
dpaa_dev = container_of(rdev, struct rte_dpaa_device,
- device);
+ device);
dev->intr_handle = dpaa_dev->intr_handle;
if (rte_intr_vec_list_alloc(dev->intr_handle,
- NULL, dpaa_push_mode_max_queue)) {
+ NULL, dpaa_push_queue_max_num())) {
DPAA_PMD_ERR("intr_vec alloc failed");
return -ENOMEM;
}
if (rte_intr_nb_efd_set(dev->intr_handle,
- dpaa_push_mode_max_queue))
+ dpaa_push_queue_max_num()))
return -rte_errno;
if (rte_intr_max_intr_set(dev->intr_handle,
- dpaa_push_mode_max_queue))
+ dpaa_push_queue_max_num()))
return -rte_errno;
}
@@ -1339,9 +1329,8 @@ int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
RTE_EXPORT_INTERNAL_SYMBOL(dpaa_eth_eventq_attach)
int
dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
- int eth_rx_queue_id,
- u16 ch_id,
- const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
+ int eth_rx_queue_id, u16 ch_id,
+ const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
{
int ret;
u32 flags = 0;
@@ -1349,10 +1338,10 @@ dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
struct qm_mcc_initfq opts = {0};
- if (dpaa_push_mode_max_queue) {
+ if (dpaa_push_queue_max_num() > 0) {
DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible");
DPAA_PMD_WARN("PUSH mode already enabled for first %d queues.",
- dpaa_push_mode_max_queue);
+ dpaa_push_queue_max_num());
DPAA_PMD_WARN("To disable set DPAA_PUSH_QUEUES_NUMBER to 0");
}
@@ -2581,20 +2570,6 @@ rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv,
}
}
- /* disabling the default push mode for LS1043 */
- if (dpaa_soc_ver() == SVR_LS1043A_FAMILY)
- dpaa_push_mode_max_queue = 0;
-
- /* if push mode queues to be enabled. Currently we are allowing
- * only one queue per thread.
- */
- if (getenv("DPAA_PUSH_QUEUES_NUMBER")) {
- dpaa_push_mode_max_queue =
- atoi(getenv("DPAA_PUSH_QUEUES_NUMBER"));
- if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE)
- dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE;
- }
-
is_global_init = 1;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 5/5] net/dpaa: Fix coverity issue
2025-10-08 4:35 ` [PATCH v2 0/5] DPAA specific changes Gagandeep Singh
` (3 preceding siblings ...)
2025-10-08 4:35 ` [PATCH v2 4/5] bus/dpaa: Set max push RXQ number Gagandeep Singh
@ 2025-10-08 4:35 ` Gagandeep Singh
4 siblings, 0 replies; 12+ messages in thread
From: Gagandeep Singh @ 2025-10-08 4:35 UTC (permalink / raw)
To: dev, Hemant Agrawal, Sachin Saxena; +Cc: Vanshika Shukla
From: Vanshika Shukla <vanshika.shukla@nxp.com>
Fix Resource leak CID:362787 issue reported by external coverity tool.
Signed-off-by: Vanshika Shukla <vanshika.shukla@nxp.com>
---
drivers/net/dpaa/dpaa_flow.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/dpaa/dpaa_flow.c b/drivers/net/dpaa/dpaa_flow.c
index 2a22b23c8f..417b9b6fbb 100644
--- a/drivers/net/dpaa/dpaa_flow.c
+++ b/drivers/net/dpaa/dpaa_flow.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright 2017-2019,2021-2024 NXP
+ * Copyright 2017-2019,2021-2025 NXP
*/
/* System headers */
@@ -889,9 +889,9 @@ int dpaa_fm_init(void)
/* FM PCD Enable */
ret = fm_pcd_enable(pcd_handle);
if (ret) {
- fm_close(fman_handle);
- fm_pcd_close(pcd_handle);
DPAA_PMD_ERR("fm_pcd_enable: Failed");
+ fm_pcd_close(pcd_handle);
+ fm_close(fman_handle);
return -1;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread