[PATCH 07/15] net/dpaa2: add dpmac MC header file

[PATCH 07/15] net/dpaa2: add dpmac MC header file

[Prashant Gupta]

This patch upgrades the MC firmware release API compatibility
to 10.39.0. Added mc/fsl_dpmac.h file.

Signed-off-by: Prashant Gupta <prashant.gupta_3@nxp.com>
---
 drivers/net/dpaa2/mc/fsl_dpmac.h | 465 +++++++++++++++++++++++++++++++
 1 file changed, 465 insertions(+)
 create mode 100644 drivers/net/dpaa2/mc/fsl_dpmac.h

diff --git a/drivers/net/dpaa2/mc/fsl_dpmac.h b/drivers/net/dpaa2/mc/fsl_dpmac.h
new file mode 100644
index 0000000000..41eca47cfa
--- /dev/null
+++ b/drivers/net/dpaa2/mc/fsl_dpmac.h
@@ -0,0 +1,465 @@
+/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
+ *
+ * Copyright 2013-2016 Freescale Semiconductor Inc.
+ * Copyright 2018-2025 NXP
+ *
+ */
+
+#ifndef __FSL_DPMAC_H
+#define __FSL_DPMAC_H
+
+/** @addtogroup dpmac Data Path MAC API
+ * Contains initialization APIs and runtime control APIs for DPMAC
+ * @{
+ */
+
+struct fsl_mc_io;
+
+int dpmac_open(struct fsl_mc_io *mc_io,
+	       uint32_t cmd_flags,
+	       int dpmac_id,
+	       uint16_t *token);
+
+int dpmac_close(struct fsl_mc_io *mc_io,
+		uint32_t cmd_flags,
+		uint16_t token);
+
+/**
+ * enum dpmac_link_type -  DPMAC link type
+ * @DPMAC_LINK_TYPE_NONE: No link
+ * @DPMAC_LINK_TYPE_FIXED: Link is fixed type
+ * @DPMAC_LINK_TYPE_PHY: Link by PHY ID
+ * @DPMAC_LINK_TYPE_BACKPLANE: Backplane link type
+ */
+enum dpmac_link_type {
+	DPMAC_LINK_TYPE_NONE,
+	DPMAC_LINK_TYPE_FIXED,
+	DPMAC_LINK_TYPE_PHY,
+	DPMAC_LINK_TYPE_BACKPLANE
+};
+
+/**
+ * enum dpmac_eth_if - DPMAC Ethrnet interface
+ * @DPMAC_ETH_IF_MII: MII interface
+ * @DPMAC_ETH_IF_RMII: RMII interface
+ * @DPMAC_ETH_IF_SMII: SMII interface
+ * @DPMAC_ETH_IF_GMII: GMII interface
+ * @DPMAC_ETH_IF_RGMII: RGMII interface
+ * @DPMAC_ETH_IF_SGMII: SGMII interface
+ * @DPMAC_ETH_IF_QSGMII: QSGMII interface
+ * @DPMAC_ETH_IF_XAUI: XAUI interface
+ * @DPMAC_ETH_IF_XFI: XFI interface
+ * @DPMAC_ETH_IF_CAUI: CAUI interface
+ * @DPMAC_ETH_IF_1000BASEX: 1000BASEX interface
+ * @DPMAC_ETH_IF_USXGMII: USXGMII interface
+ */
+enum dpmac_eth_if {
+	DPMAC_ETH_IF_MII,
+	DPMAC_ETH_IF_RMII,
+	DPMAC_ETH_IF_SMII,
+	DPMAC_ETH_IF_GMII,
+	DPMAC_ETH_IF_RGMII,
+	DPMAC_ETH_IF_SGMII,
+	DPMAC_ETH_IF_QSGMII,
+	DPMAC_ETH_IF_XAUI,
+	DPMAC_ETH_IF_XFI,
+	DPMAC_ETH_IF_CAUI,
+	DPMAC_ETH_IF_1000BASEX,
+	DPMAC_ETH_IF_USXGMII,
+};
+/*
+ * @DPMAC_FEC_NONE: RS-FEC (enabled by default) is disabled
+ * @DPMAC_FEC_RS: RS-FEC (Clause 91) mode configured
+ * @DPMAC_FEC_FC: FC-FEC (Clause 74) mode configured (not yet supported)
+ */
+enum dpmac_fec_mode {
+	DPMAC_FEC_NONE,
+	DPMAC_FEC_RS,
+	DPMAC_FEC_FC,
+};
+
+/* serdes sfi/custom settings feature internals
+ * @SERDES_CFG_DEFAULT: the default configuration.
+ * @SERDES_CFG_SFI: default operating mode for XFI interfaces
+ * @SERDES_CFG_CUSTOM: It allows the user to manually configure the type of equalization,
+ *	amplitude, preq and post1q settings. Can be used with all interfaces except RGMII.
+ */
+enum serdes_eq_cfg_mode {
+	SERDES_CFG_DEFAULT = 0,
+	SERDES_CFG_SFI,
+	SERDES_CFG_CUSTOM,
+};
+
+/**
+ * struct dpmac_cfg - Structure representing DPMAC configuration
+ * @mac_id:	Represents the Hardware MAC ID; in case of multiple WRIOP,
+ *		the MAC IDs are continuous.
+ *		For example:  2 WRIOPs, 16 MACs in each:
+ *				MAC IDs for the 1st WRIOP: 1-16,
+ *				MAC IDs for the 2nd WRIOP: 17-32.
+ */
+struct dpmac_cfg {
+	uint16_t mac_id;
+};
+
+int dpmac_create(struct fsl_mc_io *mc_io,
+		 uint16_t dprc_token,
+		 uint32_t cmd_flags,
+		 const struct dpmac_cfg *cfg,
+		 uint32_t *obj_id);
+
+int dpmac_destroy(struct fsl_mc_io *mc_io,
+		  uint16_t dprc_token,
+		  uint32_t cmd_flags,
+		  uint32_t object_id);
+
+/**
+ * DPMAC IRQ Index and Events
+ */
+
+/**
+ * IRQ index
+ */
+#define DPMAC_IRQ_INDEX				0
+/**
+ * IRQ event - indicates a change in link state
+ */
+#define DPMAC_IRQ_EVENT_LINK_CFG_REQ		0x00000001
+/**
+ * IRQ event - Indicates that the link state changed
+ */
+#define DPMAC_IRQ_EVENT_LINK_CHANGED		0x00000002
+/**
+ * IRQ event - The object requests link up
+ */
+#define DPMAC_IRQ_EVENT_LINK_UP_REQ			0x00000004
+/**
+ * IRQ event - The object requests link down
+ */
+#define DPMAC_IRQ_EVENT_LINK_DOWN_REQ		0x00000008
+/**
+ * IRQ event - indicates a change in endpoint
+ */
+#define DPMAC_IRQ_EVENT_ENDPOINT_CHANGED	0x00000010
+
+int dpmac_set_irq_enable(struct fsl_mc_io *mc_io,
+			 uint32_t cmd_flags,
+			 uint16_t token,
+			 uint8_t irq_index,
+			 uint8_t en);
+
+int dpmac_get_irq_enable(struct fsl_mc_io *mc_io,
+			 uint32_t cmd_flags,
+			 uint16_t token,
+			 uint8_t irq_index,
+			 uint8_t *en);
+
+int dpmac_set_irq_mask(struct fsl_mc_io *mc_io,
+		       uint32_t cmd_flags,
+		       uint16_t token,
+		       uint8_t irq_index,
+		       uint32_t mask);
+
+int dpmac_get_irq_mask(struct fsl_mc_io *mc_io,
+		       uint32_t cmd_flags,
+		       uint16_t token,
+		       uint8_t irq_index,
+		       uint32_t *mask);
+
+int dpmac_get_irq_status(struct fsl_mc_io *mc_io,
+			 uint32_t cmd_flags,
+			 uint16_t token,
+			 uint8_t irq_index,
+			 uint32_t *status);
+
+int dpmac_clear_irq_status(struct fsl_mc_io *mc_io,
+			   uint32_t cmd_flags,
+			   uint16_t token,
+			   uint8_t irq_index,
+			   uint32_t status);
+
+/**
+ * @brief	Inter-Frame Gap mode
+ *
+ * LAN/WAN uses different Inter-Frame Gap mode
+ */
+enum dpmac_ifg_mode {
+	DPMAC_IFG_MODE_FIXED,
+	/*!< IFG length represents number of octets in steps of 4 */
+	DPMAC_IFG_MODE_STRETCHED
+	/*!< IFG length represents the stretch factor */
+};
+
+/**
+ * @brief Structure representing Inter-Frame Gap mode configuration
+ */
+struct dpmac_ifg_cfg {
+	enum dpmac_ifg_mode ipg_mode; /*!< WAN/LAN mode */
+	uint8_t ipg_length; /*!< IPG Length, default value is 0xC */
+};
+
+/**
+ * @brief Structure used to read through MDIO
+ */
+struct dpmac_mdio_read {
+	uint8_t cl45; /*!< Clause 45 */
+	uint8_t phy_addr; /*!< MDIO PHY address */
+	uint16_t reg; /*!< PHY register */
+};
+
+/**
+ * @brief Structure used to write through MDIO
+ */
+struct dpmac_mdio_write {
+	uint8_t cl45; /*!< Clause 45 */
+	uint8_t phy_addr; /*!< MDIO PHY address */
+	uint16_t reg; /*!< PHY register */
+	uint16_t data; /*!< Data to be written */
+};
+
+#define DPMAC_SET_PARAMS_IFG 0x1
+
+/**
+ * struct serdes_eq_settings - Structure  SerDes equalization settings
+ * cfg: serdes sfi/custom/default settings feature internals
+ * @eq_type: Number of levels of TX equalization
+ * @sgn_preq: Precursor sign indicating direction of eye closure
+ * @eq_preq: Drive strength of TX full swing transition bit to precursor
+ * @sgn_post1q: First post-cursor sign indicating direction of eye closure
+ * @eq_post1q: Drive strength of full swing transition bit to first post-cursor
+ * @eq_amp_red: Overall transmit amplitude reduction
+ */
+struct serdes_eq_settings {
+	enum serdes_eq_cfg_mode cfg;
+	int eq_type;
+	int sgn_preq;
+	int eq_preq;
+	int sgn_post1q;
+	int eq_post1q;
+	int eq_amp_red;
+};
+
+/**
+ * struct dpmac_attr - Structure representing DPMAC attributes
+ * @id:		DPMAC object ID
+ * @max_rate:	Maximum supported rate - in Mbps
+ * @eth_if:	Ethernet interface
+ * @link_type:	link type
+ * @fec_mode:	FEC mode - Configurable only for 25G interfaces
+ * serdes_cfg:	SerDes equalization settings
+ */
+struct dpmac_attr {
+	uint16_t id;
+	uint32_t max_rate;
+	enum dpmac_eth_if eth_if;
+	enum dpmac_link_type link_type;
+	enum dpmac_fec_mode fec_mode;
+	struct serdes_eq_settings serdes_cfg;
+	struct dpmac_ifg_cfg ifg_cfg;
+};
+
+int dpmac_get_attributes(struct fsl_mc_io *mc_io,
+			 uint32_t cmd_flags,
+			 uint16_t token,
+			 struct dpmac_attr *attr);
+
+int dpmac_set_params(struct fsl_mc_io *mc_io,
+		       uint32_t cmd_flags,
+		       uint16_t token,
+			   uint32_t flags,
+			   struct dpmac_ifg_cfg ifg_cfg);
+
+int dpmac_get_mac_addr(struct fsl_mc_io *mc_io,
+			   uint32_t cmd_flags,
+			   uint16_t token,
+			   uint8_t mac_addr[6]);
+
+/**
+ * DPMAC link configuration/state options
+ */
+
+/**
+ * Enable auto-negotiation
+ */
+#define DPMAC_LINK_OPT_AUTONEG		0x0000000000000001ULL
+/**
+ * Enable half-duplex mode
+ */
+#define DPMAC_LINK_OPT_HALF_DUPLEX	0x0000000000000002ULL
+/**
+ * Enable pause frames
+ */
+#define DPMAC_LINK_OPT_PAUSE		0x0000000000000004ULL
+/**
+ * Enable a-symmetric pause frames
+ */
+#define DPMAC_LINK_OPT_ASYM_PAUSE	0x0000000000000008ULL
+/**
+ * Advertise 10MB full duplex
+ */
+#define DPMAC_ADVERTISED_10BASET_FULL           0x0000000000000001ULL
+/**
+ * Advertise 100MB full duplex
+ */
+#define DPMAC_ADVERTISED_100BASET_FULL          0x0000000000000002ULL
+/**
+ * Advertise 1GB full duplex
+ */
+#define DPMAC_ADVERTISED_1000BASET_FULL         0x0000000000000004ULL
+/**
+ * Advertise auto-negotiation enable
+ */
+#define DPMAC_ADVERTISED_AUTONEG                0x0000000000000008ULL
+/**
+ * Advertise 10GB full duplex
+ */
+#define DPMAC_ADVERTISED_10000BASET_FULL        0x0000000000000010ULL
+/**
+ * Advertise 2.5GB full duplex
+ */
+#define DPMAC_ADVERTISED_2500BASEX_FULL         0x0000000000000020ULL
+/**
+ * Advertise 5GB full duplex
+ */
+#define DPMAC_ADVERTISED_5000BASET_FULL         0x0000000000000040ULL
+
+/**
+ * struct dpmac_link_cfg - Structure representing DPMAC link configuration
+ * @rate: Link's rate - in Mbps
+ * @options: Enable/Disable DPMAC link cfg features (bitmap)
+ * @advertising: Speeds that are advertised for autoneg (bitmap)
+ */
+struct dpmac_link_cfg {
+	uint32_t rate;
+	uint64_t options;
+	uint64_t advertising;
+};
+
+int dpmac_get_link_cfg(struct fsl_mc_io *mc_io,
+		       uint32_t cmd_flags,
+		       uint16_t token,
+		       struct dpmac_link_cfg *cfg);
+
+/**
+ * struct dpmac_link_state - DPMAC link configuration request
+ * @rate: Rate in Mbps
+ * @options: Enable/Disable DPMAC link cfg features (bitmap)
+ * @up: Link state
+ * @state_valid: Ignore/Update the state of the link
+ * @supported: Speeds capability of the phy (bitmap)
+ * @advertising: Speeds that are advertised for autoneg (bitmap)
+ */
+struct dpmac_link_state {
+	uint32_t rate;
+	uint64_t options;
+	int up;
+	int state_valid;
+	uint64_t supported;
+	uint64_t advertising;
+};
+
+int dpmac_set_link_state(struct fsl_mc_io *mc_io,
+			 uint32_t cmd_flags,
+			 uint16_t token,
+			 struct dpmac_link_state *link_state);
+
+/**
+ * enum dpmac_counter - DPMAC counter types
+ * @DPMAC_CNT_ING_FRAME_64: counts 64-bytes frames, good or bad.
+ * @DPMAC_CNT_ING_FRAME_127: counts 65- to 127-bytes frames, good or bad.
+ * @DPMAC_CNT_ING_FRAME_255: counts 128- to 255-bytes frames, good or bad.
+ * @DPMAC_CNT_ING_FRAME_511: counts 256- to 511-bytes frames, good or bad.
+ * @DPMAC_CNT_ING_FRAME_1023: counts 512- to 1023-bytes frames, good or bad.
+ * @DPMAC_CNT_ING_FRAME_1518: counts 1024- to 1518-bytes frames, good or bad.
+ * @DPMAC_CNT_ING_FRAME_1519_MAX: counts 1519-bytes frames and larger
+ *				  (up to max frame length specified),
+ *				  good or bad.
+ * @DPMAC_CNT_ING_FRAG: counts frames which are shorter than 64 bytes received
+ *			with a wrong CRC
+ * @DPMAC_CNT_ING_JABBER: counts frames longer than the maximum frame length
+ *			  specified, with a bad frame check sequence.
+ * @DPMAC_CNT_ING_FRAME_DISCARD: counts dropped frames due to internal errors.
+ *				 Occurs when a receive FIFO overflows.
+ *				 Includes also frames truncated as a result of
+ *				 the receive FIFO overflow.
+ * @DPMAC_CNT_ING_ALIGN_ERR: counts frames with an alignment error
+ *			     (optional used for wrong SFD).
+ * @DPMAC_CNT_EGR_UNDERSIZED: counts frames transmitted that was less than 64
+ *			      bytes long with a good CRC.
+ * @DPMAC_CNT_ING_OVERSIZED: counts frames longer than the maximum frame length
+ *			     specified, with a good frame check sequence.
+ * @DPMAC_CNT_ING_VALID_PAUSE_FRAME: counts valid pause frames (regular and PFC)
+ * @DPMAC_CNT_EGR_VALID_PAUSE_FRAME: counts valid pause frames transmitted
+ *				     (regular and PFC).
+ * @DPMAC_CNT_ING_BYTE: counts bytes received except preamble for all valid
+ *			frames and valid pause frames.
+ * @DPMAC_CNT_ING_MCAST_FRAME: counts received multicast frames.
+ * @DPMAC_CNT_ING_BCAST_FRAME: counts received broadcast frames.
+ * @DPMAC_CNT_ING_ALL_FRAME: counts each good or bad frames received.
+ * @DPMAC_CNT_ING_UCAST_FRAME: counts received unicast frames.
+ * @DPMAC_CNT_ING_ERR_FRAME: counts frames received with an error
+ *			     (except for undersized/fragment frame).
+ * @DPMAC_CNT_EGR_BYTE: counts bytes transmitted except preamble for all valid
+ *			frames and valid pause frames transmitted.
+ * @DPMAC_CNT_EGR_MCAST_FRAME: counts transmitted multicast frames.
+ * @DPMAC_CNT_EGR_BCAST_FRAME: counts transmitted broadcast frames.
+ * @DPMAC_CNT_EGR_UCAST_FRAME: counts transmitted unicast frames.
+ * @DPMAC_CNT_EGR_ERR_FRAME: counts frames transmitted with an error.
+ * @DPMAC_CNT_ING_GOOD_FRAME: counts frames received without error, including
+ *			      pause frames.
+ * @DPMAC_CNT_EGR_GOOD_FRAME: counts frames transmitted without error, including
+ *			      pause frames.
+ */
+enum dpmac_counter {
+	DPMAC_CNT_ING_FRAME_64,
+	DPMAC_CNT_ING_FRAME_127,
+	DPMAC_CNT_ING_FRAME_255,
+	DPMAC_CNT_ING_FRAME_511,
+	DPMAC_CNT_ING_FRAME_1023,
+	DPMAC_CNT_ING_FRAME_1518,
+	DPMAC_CNT_ING_FRAME_1519_MAX,
+	DPMAC_CNT_ING_FRAG,
+	DPMAC_CNT_ING_JABBER,
+	DPMAC_CNT_ING_FRAME_DISCARD,
+	DPMAC_CNT_ING_ALIGN_ERR,
+	DPMAC_CNT_EGR_UNDERSIZED,
+	DPMAC_CNT_ING_OVERSIZED,
+	DPMAC_CNT_ING_VALID_PAUSE_FRAME,
+	DPMAC_CNT_EGR_VALID_PAUSE_FRAME,
+	DPMAC_CNT_ING_BYTE,
+	DPMAC_CNT_ING_MCAST_FRAME,
+	DPMAC_CNT_ING_BCAST_FRAME,
+	DPMAC_CNT_ING_ALL_FRAME,
+	DPMAC_CNT_ING_UCAST_FRAME,
+	DPMAC_CNT_ING_ERR_FRAME,
+	DPMAC_CNT_EGR_BYTE,
+	DPMAC_CNT_EGR_MCAST_FRAME,
+	DPMAC_CNT_EGR_BCAST_FRAME,
+	DPMAC_CNT_EGR_UCAST_FRAME,
+	DPMAC_CNT_EGR_ERR_FRAME,
+	DPMAC_CNT_ING_GOOD_FRAME,
+	DPMAC_CNT_EGR_GOOD_FRAME
+};
+
+int dpmac_get_counter(struct fsl_mc_io *mc_io,
+		      uint32_t cmd_flags,
+		      uint16_t token,
+		      enum dpmac_counter  type,
+		      uint64_t *counter);
+
+int dpmac_get_api_version(struct fsl_mc_io *mc_io,
+			  uint32_t cmd_flags,
+			  uint16_t *major_ver,
+			  uint16_t *minor_ver);
+
+int dpmac_reset(struct fsl_mc_io *mc_io,
+		uint32_t cmd_flags,
+		uint16_t token);
+
+int dpmac_set_protocol(struct fsl_mc_io *mc_io, uint32_t cmd_flags,
+		       uint16_t token, enum dpmac_eth_if protocol);
+
+int dpmac_get_statistics(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token,
+			 uint64_t iova_cnt, uint64_t iova_values, uint32_t num_cnt);
+
+#endif /* __FSL_DPMAC_H */
-- 
2.43.0

[PATCH 00/15] dpaa2: Fixes and enhancements for DPMAC, stats, and parser

[Prashant Gupta]

From: Prashant Gupta <nxg06376@lsv03583.swis.in-blr01.nxp.com>

This patch series introduces a set of improvements and bug fixes for the DPAA2 Ethernet driver. Key highlights include:

- Fixes for checksum parsing and error queue buffer handling
- Enhancements to flow rule resizing and parser result prefetching
- Addition of DPMAC MC header support and Policer statistics per traffic class
- Support for eCPRI header/message dump and DPMAC counters
- Upgrade of fslmc base firmware to version 10.39.0
- Introduction of devargs to drop parse-failed packets in hardware

These changes improve robustness, observability, and performance of the DPAA2 driver stack.


Brick Yang (2):
  net/dpaa2: fix L3/L4 csum results in packet parse
  net/dpaa2: fix to recv packets with additional parse errors

Hemant Agrawal (3):
  drivers: dpaa2 upgrade fslmc base FW to 10.39.0
  net/dpaa2: replace global variable to driver flag
  net/dpaa2: add devargs to drop parse packets in HW

Ioana Ciornei (1):
  net/dpaa2: setup the speed cap based on the actual MAC

Jun Yang (4):
  net/dpaa2: fix error frame dump issue
  net/dpaa2: fix flow rule's resizing issue
  net/dpaa2: optimize to prefetch next parser result
  net/dpaa2: add eCPRI header and message dump

Prashant Gupta (4):
  net/dpaa2: fix uninitialized variable issue
  net/dpaa2: fix to free buffers from error queue
  net/dpaa2: add dpmac MC header file
  net/dpaa2: add Policer stats for each TC

Vanshika Shukla (1):
  net/dpaa2: support dpmac counters in stats

 .mailmap                                     |   1 +
 doc/guides/nics/dpaa2.rst                    |   4 +
 doc/guides/rel_notes/release_25_11.rst       |   3 +
 drivers/bus/fslmc/bus_fslmc_driver.h         |   1 +
 drivers/bus/fslmc/mc/dpbp.c                  |  78 ++-
 drivers/bus/fslmc/mc/dprc.c                  |   2 +
 drivers/bus/fslmc/mc/fsl_dpbp.h              |  41 +-
 drivers/bus/fslmc/mc/fsl_dpmng.h             |   4 +-
 drivers/bus/fslmc/mc/fsl_dprc.h              |   1 +
 drivers/net/dpaa2/base/dpaa2_hw_dpni.c       |   3 +-
 drivers/net/dpaa2/base/dpaa2_hw_dpni_annot.h |  10 +-
 drivers/net/dpaa2/dpaa2_ethdev.c             | 350 +++++++++++-
 drivers/net/dpaa2/dpaa2_ethdev.h             |  65 ++-
 drivers/net/dpaa2/dpaa2_flow.c               | 123 ++++-
 drivers/net/dpaa2/dpaa2_mux.c                |   8 +-
 drivers/net/dpaa2/dpaa2_parse_dump.h         | 124 +++++
 drivers/net/dpaa2/dpaa2_rxtx.c               | 124 +++--
 drivers/net/dpaa2/mc/dpkg.c                  |   7 +-
 drivers/net/dpaa2/mc/dpni.c                  |  50 +-
 drivers/net/dpaa2/mc/dprtc.c                 |  38 +-
 drivers/net/dpaa2/mc/fsl_dpdmux.h            |  13 +-
 drivers/net/dpaa2/mc/fsl_dpkg.h              |   7 +-
 drivers/net/dpaa2/mc/fsl_dpmac.h             | 526 +++++++++++++++++++
 drivers/net/dpaa2/mc/fsl_dpni.h              |  37 +-
 drivers/net/dpaa2/mc/fsl_dpni_cmd.h          |  15 +-
 drivers/net/dpaa2/mc/fsl_dprtc.h             |  39 +-
 drivers/net/dpaa2/mc/fsl_dprtc_cmd.h         |   7 +-
 27 files changed, 1518 insertions(+), 163 deletions(-)
 create mode 100644 drivers/net/dpaa2/mc/fsl_dpmac.h

-- 
2.25.1

[PATCH 01/15] net/dpaa2: fix uninitialized variable issue

[Prashant Gupta]

Initialize the kg_cfg structure before use in
rte_pmd_dpaa2_set_custom_hash(). This resolves an issue with
uninitialized memory access.

Fixes: 5f822962498e ("net/dpaa2: support custom hash key")
Cc: stable@dpdk.org

Signed-off-by: Prashant Gupta <prashant.gupta_3@nxp.com>
---
 .mailmap                               | 1 +
 drivers/net/dpaa2/base/dpaa2_hw_dpni.c | 3 ++-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/.mailmap b/.mailmap
index 0b043cb0c0..c260830f20 100644
--- a/.mailmap
+++ b/.mailmap
@@ -1261,6 +1261,7 @@ Piotr Skajewski <piotrx.skajewski@intel.com>
 Potnuri Bharat Teja <bharat@chelsio.com>
 Pradeep Satyanarayana <pradeep@us.ibm.com>
 Prashant Bhole <bhole_prashant_q7@lab.ntt.co.jp>
+Prashant Gupta <prashant.gupta_3@nxp.com>
 Prashant Upadhyaya <prashant.upadhyaya@aricent.com> <praupadhyaya@gmail.com>
 Prateek Agarwal <prateekag@cse.iitb.ac.in>
 Prathisna Padmasanan <prathisna.padmasanan@intel.com>
diff --git a/drivers/net/dpaa2/base/dpaa2_hw_dpni.c b/drivers/net/dpaa2/base/dpaa2_hw_dpni.c
index b1d473429a..13825046d8 100644
--- a/drivers/net/dpaa2/base/dpaa2_hw_dpni.c
+++ b/drivers/net/dpaa2/base/dpaa2_hw_dpni.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  *
  *   Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
- *   Copyright 2016-2021,2023-2024 NXP
+ *   Copyright 2016-2021,2023-2025 NXP
  *
  */
 
@@ -60,6 +60,7 @@ rte_pmd_dpaa2_set_custom_hash(uint16_t port_id,
 		return -ENOMEM;
 	}
 
+	memset(&kg_cfg, 0, sizeof(struct dpkg_profile_cfg));
 	kg_cfg.extracts[0].type = DPKG_EXTRACT_FROM_DATA;
 	kg_cfg.extracts[0].extract.from_data.offset = offset;
 	kg_cfg.extracts[0].extract.from_data.size = size;
-- 
2.43.0

[PATCH 02/15] net/dpaa2: fix to free buffers from error queue

[Prashant Gupta]

Free a packet mbuf back into its original mempool.
Fixes: 4690a6114ff6 ("net/dpaa2: enable error queues optionally")
Cc: stable@dpdk.org

Signed-off-by: Prashant Gupta <prashant.gupta_3@nxp.com>
---
 drivers/net/dpaa2/dpaa2_rxtx.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/dpaa2/dpaa2_rxtx.c b/drivers/net/dpaa2/dpaa2_rxtx.c
index 5bd377d4e6..656a3a423f 100644
--- a/drivers/net/dpaa2/dpaa2_rxtx.c
+++ b/drivers/net/dpaa2/dpaa2_rxtx.c
@@ -708,6 +708,7 @@ dump_err_pkts(struct dpaa2_queue *dpaa2_q)
 		rte_hexdump(stderr, "Error packet", v_addr,
 			DPAA2_GET_FD_OFFSET(fd) + DPAA2_GET_FD_LEN(fd));
 
+		rte_pktmbuf_free(mbuf);
 		dq_storage++;
 		num_rx++;
 	} while (pending);
-- 
2.43.0

[PATCH 03/15] net/dpaa2: fix L3/L4 csum results in packet parse

[Prashant Gupta]

From: Brick Yang <brick.yang@nxp.com>

Layer3 and layer4 checksum validation and error
status is part of word1 of annotation area, but
driver is looking into wrong word.
This patch fixes the checksum error status in packet
parsing.

Fixes: 94d31549c380 ("net/dpaa2: support Rx checksum offload in slow parsing")
Cc: stable@dpdk.org

Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
Signed-off-by: Brick Yang <brick.yang@nxp.com>
---
 drivers/net/dpaa2/base/dpaa2_hw_dpni_annot.h | 10 +++++-----
 drivers/net/dpaa2/dpaa2_rxtx.c               | 17 ++---------------
 2 files changed, 7 insertions(+), 20 deletions(-)

diff --git a/drivers/net/dpaa2/base/dpaa2_hw_dpni_annot.h b/drivers/net/dpaa2/base/dpaa2_hw_dpni_annot.h
index d156b07087..a670098958 100644
--- a/drivers/net/dpaa2/base/dpaa2_hw_dpni_annot.h
+++ b/drivers/net/dpaa2/base/dpaa2_hw_dpni_annot.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  *
  *   Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
- *   Copyright 2016,2019 NXP
+ *   Copyright 2016,2019,2022,2024 NXP
  *
  */
 
@@ -304,13 +304,13 @@ struct dpaa2_faead {
 #define DPAA2_ETH_FAS_PHE	       0x00000020
 #define DPAA2_ETH_FAS_BLE	       0x00000010
 /* L3 csum validation performed */
-#define DPAA2_ETH_FAS_L3CV	      0x00000008
+#define DPAA2_ETH_FAS_L3CV	      0x0000000800000000
 /* L3 csum error */
-#define DPAA2_ETH_FAS_L3CE	      0x00000004
+#define DPAA2_ETH_FAS_L3CE	      0x0000000400000000
 /* L4 csum validation performed */
-#define DPAA2_ETH_FAS_L4CV	      0x00000002
+#define DPAA2_ETH_FAS_L4CV	      0x0000000200000000
 /* L4 csum error */
-#define DPAA2_ETH_FAS_L4CE	      0x00000001
+#define DPAA2_ETH_FAS_L4CE	      0x0000000100000000
 
 #ifdef __cplusplus
 }
diff --git a/drivers/net/dpaa2/dpaa2_rxtx.c b/drivers/net/dpaa2/dpaa2_rxtx.c
index 656a3a423f..6cb91e67d4 100644
--- a/drivers/net/dpaa2/dpaa2_rxtx.c
+++ b/drivers/net/dpaa2/dpaa2_rxtx.c
@@ -201,14 +201,10 @@ dpaa2_dev_rx_parse_slow(struct rte_mbuf *mbuf,
 		goto parse_done;
 	}
 
-	if (BIT_ISSET_AT_POS(annotation->word8, DPAA2_ETH_FAS_L3CE))
+	if (BIT_ISSET_AT_POS(annotation->word1, DPAA2_ETH_FAS_L3CE))
 		mbuf->ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
-	else
-		mbuf->ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
-	if (BIT_ISSET_AT_POS(annotation->word8, DPAA2_ETH_FAS_L4CE))
+	else if (BIT_ISSET_AT_POS(annotation->word1, DPAA2_ETH_FAS_L4CE))
 		mbuf->ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
-	else
-		mbuf->ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
 
 	if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_1_FIRST_FRAGMENT |
 	    L3_IP_1_MORE_FRAGMENT |
@@ -248,15 +244,6 @@ dpaa2_dev_rx_parse(struct rte_mbuf *mbuf, void *hw_annot_addr)
 	DPAA2_PMD_DP_DEBUG("(fast parse) Annotation = 0x%" PRIx64 "\t",
 			   annotation->word4);
 
-	if (BIT_ISSET_AT_POS(annotation->word8, DPAA2_ETH_FAS_L3CE))
-		mbuf->ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
-	else
-		mbuf->ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
-	if (BIT_ISSET_AT_POS(annotation->word8, DPAA2_ETH_FAS_L4CE))
-		mbuf->ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
-	else
-		mbuf->ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
-
 	if (unlikely(dpaa2_print_parser_result))
 		dpaa2_print_parse_result(annotation);
 
-- 
2.43.0

[PATCH 04/15] net/dpaa2: fix to recv packets with additional parse errors

[Prashant Gupta]

From: Brick Yang <brick.yang@nxp.com>

Also receive packets with HW parser length errors.
Thus this option allow to let HW drop packets for any kind of parser
errors.

Fixes: 4690a6114ff6 ("net/dpaa2: enable error queues optionally")
Cc: stable@dpdk.org

Signed-off-by: Brick Yang <brick.yang@nxp.com>
---
 drivers/net/dpaa2/dpaa2_ethdev.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c
index 41678ce09b..0fd577c448 100644
--- a/drivers/net/dpaa2/dpaa2_ethdev.c
+++ b/drivers/net/dpaa2/dpaa2_ethdev.c
@@ -1240,7 +1240,7 @@ dpaa2_dev_start(struct rte_eth_dev *dev)
 		err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE;
 
 		/* if packet with parse error are not to be dropped */
-		err_cfg.errors |= DPNI_ERROR_PHE;
+		err_cfg.errors |= DPNI_ERROR_PHE | DPNI_ERROR_BLE;
 
 		err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE;
 	}
-- 
2.43.0

[PATCH 05/15] net/dpaa2: fix error frame dump issue

[Prashant Gupta]

From: Jun Yang <jun.yang@nxp.com>

Dump error frame payload according to mbuf format.
Meanwhile, support dumping parser result of error frame.

Fixes: 4690a6114ff6 ("net/dpaa2: enable error queues optionally")
Cc: stable@dpdk.org

Signed-off-by: Jun Yang <jun.yang@nxp.com>
---
 drivers/net/dpaa2/dpaa2_rxtx.c | 38 ++++++++++++++++++++++++++++------
 1 file changed, 32 insertions(+), 6 deletions(-)

diff --git a/drivers/net/dpaa2/dpaa2_rxtx.c b/drivers/net/dpaa2/dpaa2_rxtx.c
index 6cb91e67d4..7caccfa469 100644
--- a/drivers/net/dpaa2/dpaa2_rxtx.c
+++ b/drivers/net/dpaa2/dpaa2_rxtx.c
@@ -629,9 +629,11 @@ dump_err_pkts(struct dpaa2_queue *dpaa2_q)
 	const struct qbman_fd *fd;
 	struct qbman_pull_desc pulldesc;
 	struct rte_eth_dev_data *eth_data = dpaa2_q->eth_data;
-	uint32_t lcore_id = rte_lcore_id();
+	uint32_t lcore_id = rte_lcore_id(), i = 0;
 	void *v_addr, *hw_annot_addr;
 	struct dpaa2_fas *fas;
+	struct rte_mbuf *mbuf;
+	char title[32];
 
 	if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
 		ret = dpaa2_affine_qbman_swp();
@@ -687,13 +689,37 @@ dump_err_pkts(struct dpaa2_queue *dpaa2_q)
 		hw_annot_addr = (void *)((size_t)v_addr + DPAA2_FD_PTA_SIZE);
 		fas = hw_annot_addr;
 
-		DPAA2_PMD_ERR("[%d] error packet on port[%d]:"
-			" fd_off: %d, fd_err: %x, fas_status: %x",
-			rte_lcore_id(), eth_data->port_id,
+		if (DPAA2_FD_GET_FORMAT(fd) == qbman_fd_sg)
+			mbuf = eth_sg_fd_to_mbuf(fd, eth_data->port_id);
+		else
+			mbuf = eth_fd_to_mbuf(fd, eth_data->port_id);
+
+		if (!dpaa2_print_parser_result) {
+			/** Don't print parse result twice.*/
+			dpaa2_print_parse_result(hw_annot_addr);
+		}
+
+		DPAA2_PMD_ERR("Err pkt on port[%d]:", eth_data->port_id);
+		DPAA2_PMD_ERR("FD offset: %d, FD err: %x, FAS status: %x",
 			DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_ERR(fd),
 			fas->status);
-		rte_hexdump(stderr, "Error packet", v_addr,
-			DPAA2_GET_FD_OFFSET(fd) + DPAA2_GET_FD_LEN(fd));
+
+		if (mbuf)
+			__rte_mbuf_sanity_check(mbuf, 1);
+		if (mbuf->nb_segs > 1) {
+			while (mbuf) {
+				sprintf(title, "Payload seg[%d]", i);
+				rte_hexdump(stderr, title,
+					(char *)mbuf->buf_addr + mbuf->data_off,
+					mbuf->data_len);
+				mbuf = mbuf->next;
+				i++;
+			}
+		} else {
+			rte_hexdump(stderr, "Payload",
+				(char *)mbuf->buf_addr + mbuf->data_off,
+				mbuf->data_len);
+		}
 
 		rte_pktmbuf_free(mbuf);
 		dq_storage++;
-- 
2.43.0

[PATCH 06/15] net/dpaa2: fix flow rule's resizing issue

[Prashant Gupta]

From: Jun Yang <jun.yang@nxp.com>

Appending new extract need resize the flow's rule.
The rule's size should start from new extract's position plus
it's size unless the position is less than rule's original size.

Fixes: 56c1817d532e ("net/dpaa2: refactor flow engine")
Cc: stable@dpdk.org

Signed-off-by: Jun Yang <jun.yang@nxp.com>
---
 drivers/net/dpaa2/dpaa2_flow.c | 123 ++++++++++++++++++++++++++-------
 1 file changed, 97 insertions(+), 26 deletions(-)

diff --git a/drivers/net/dpaa2/dpaa2_flow.c b/drivers/net/dpaa2/dpaa2_flow.c
index 299c50dcdf..2e44bff766 100644
--- a/drivers/net/dpaa2/dpaa2_flow.c
+++ b/drivers/net/dpaa2/dpaa2_flow.c
@@ -630,42 +630,42 @@ dpaa2_flow_rule_insert_hole(struct dpaa2_dev_flow *flow,
 	int offset, int size,
 	enum dpaa2_flow_dist_type dist_type)
 {
-	int end;
-
 	if (dist_type & DPAA2_FLOW_QOS_TYPE) {
-		end = flow->qos_rule_size;
-		if (end > offset) {
+		if (offset < flow->qos_rule_size) {
 			memmove(flow->qos_key_addr + offset + size,
 					flow->qos_key_addr + offset,
-					end - offset);
+					flow->qos_rule_size - offset);
 			memset(flow->qos_key_addr + offset,
 					0, size);
 
 			memmove(flow->qos_mask_addr + offset + size,
 					flow->qos_mask_addr + offset,
-					end - offset);
+					flow->qos_rule_size - offset);
 			memset(flow->qos_mask_addr + offset,
 					0, size);
+			flow->qos_rule_size += size;
+		} else {
+			flow->qos_rule_size = offset + size;
 		}
-		flow->qos_rule_size += size;
 	}
 
 	if (dist_type & DPAA2_FLOW_FS_TYPE) {
-		end = flow->fs_rule_size;
-		if (end > offset) {
+		if (offset < flow->fs_rule_size) {
 			memmove(flow->fs_key_addr + offset + size,
 					flow->fs_key_addr + offset,
-					end - offset);
+					flow->fs_rule_size - offset);
 			memset(flow->fs_key_addr + offset,
 					0, size);
 
 			memmove(flow->fs_mask_addr + offset + size,
 					flow->fs_mask_addr + offset,
-					end - offset);
+					flow->fs_rule_size - offset);
 			memset(flow->fs_mask_addr + offset,
 					0, size);
+			flow->fs_rule_size += size;
+		} else {
+			flow->fs_rule_size = offset + size;
 		}
-		flow->fs_rule_size += size;
 	}
 
 	return 0;
@@ -1485,8 +1485,9 @@ dpaa2_flow_faf_add_rule(struct dpaa2_dev_priv *priv,
 		mask_addr = flow->qos_mask_addr + offset;
 
 		if (!(*key_addr) &&
-			key_profile->ip_addr_type == IP_NONE_ADDR_EXTRACT)
-			flow->qos_rule_size++;
+			key_profile->ip_addr_type == IP_NONE_ADDR_EXTRACT &&
+			offset >= flow->qos_rule_size)
+			flow->qos_rule_size = offset + sizeof(uint8_t);
 
 		*key_addr |=  (1 << faf_bit_in_byte);
 		*mask_addr |=  (1 << faf_bit_in_byte);
@@ -1507,8 +1508,9 @@ dpaa2_flow_faf_add_rule(struct dpaa2_dev_priv *priv,
 		mask_addr = flow->fs_mask_addr + offset;
 
 		if (!(*key_addr) &&
-			key_profile->ip_addr_type == IP_NONE_ADDR_EXTRACT)
-			flow->fs_rule_size++;
+			key_profile->ip_addr_type == IP_NONE_ADDR_EXTRACT &&
+			offset >= flow->fs_rule_size)
+			flow->fs_rule_size = offset + sizeof(uint8_t);
 
 		*key_addr |=  (1 << faf_bit_in_byte);
 		*mask_addr |=  (1 << faf_bit_in_byte);
@@ -1526,6 +1528,7 @@ dpaa2_flow_pr_rule_data_set(struct dpaa2_dev_flow *flow,
 {
 	int offset;
 	uint32_t pr_field = pr_offset << 16 | pr_size;
+	char offset_info[64], size_info[64], rule_size_info[64];
 
 	offset = dpaa2_flow_extract_key_offset(key_profile,
 			DPAA2_PR_KEY, NET_PROT_NONE, pr_field);
@@ -1534,19 +1537,43 @@ dpaa2_flow_pr_rule_data_set(struct dpaa2_dev_flow *flow,
 			pr_offset, pr_size);
 		return -EINVAL;
 	}
+	sprintf(offset_info, "offset(%d)", offset);
+	sprintf(size_info, "size(%d)", pr_size);
 
 	if (dist_type & DPAA2_FLOW_QOS_TYPE) {
+		sprintf(rule_size_info, "qos rule size(%d)",
+			flow->qos_rule_size);
 		memcpy((flow->qos_key_addr + offset), key, pr_size);
 		memcpy((flow->qos_mask_addr + offset), mask, pr_size);
-		if (key_profile->ip_addr_type == IP_NONE_ADDR_EXTRACT)
-			flow->qos_rule_size = offset + pr_size;
+		if (key_profile->ip_addr_type == IP_NONE_ADDR_EXTRACT) {
+			if (offset >= flow->qos_rule_size) {
+				flow->qos_rule_size = offset + pr_size;
+			} else if ((offset + pr_size) > flow->qos_rule_size) {
+				DPAA2_PMD_ERR("%s < %s, but %s + %s > %s",
+					offset_info, rule_size_info,
+					offset_info, size_info,
+					rule_size_info);
+				return -EINVAL;
+			}
+		}
 	}
 
 	if (dist_type & DPAA2_FLOW_FS_TYPE) {
+		sprintf(rule_size_info, "fs rule size(%d)",
+			flow->fs_rule_size);
 		memcpy((flow->fs_key_addr + offset), key, pr_size);
 		memcpy((flow->fs_mask_addr + offset), mask, pr_size);
-		if (key_profile->ip_addr_type == IP_NONE_ADDR_EXTRACT)
-			flow->fs_rule_size = offset + pr_size;
+		if (key_profile->ip_addr_type == IP_NONE_ADDR_EXTRACT) {
+			if (offset >= flow->fs_rule_size) {
+				flow->fs_rule_size = offset + pr_size;
+			} else if ((offset + pr_size) > flow->fs_rule_size) {
+				DPAA2_PMD_ERR("%s < %s, but %s + %s > %s",
+					offset_info, rule_size_info,
+					offset_info, size_info,
+					rule_size_info);
+				return -EINVAL;
+			}
+		}
 	}
 
 	return 0;
@@ -1560,6 +1587,7 @@ dpaa2_flow_hdr_rule_data_set(struct dpaa2_dev_flow *flow,
 	enum dpaa2_flow_dist_type dist_type)
 {
 	int offset;
+	char offset_info[64], size_info[64], rule_size_info[64];
 
 	if (dpaa2_flow_ip_address_extract(prot, field)) {
 		DPAA2_PMD_ERR("%s only for none IP address extract",
@@ -1574,19 +1602,41 @@ dpaa2_flow_hdr_rule_data_set(struct dpaa2_dev_flow *flow,
 			prot, field);
 		return -EINVAL;
 	}
+	sprintf(offset_info, "offset(%d)", offset);
+	sprintf(size_info, "size(%d)", size);
 
 	if (dist_type & DPAA2_FLOW_QOS_TYPE) {
+		sprintf(rule_size_info, "qos rule size(%d)",
+			flow->qos_rule_size);
 		memcpy((flow->qos_key_addr + offset), key, size);
 		memcpy((flow->qos_mask_addr + offset), mask, size);
-		if (key_profile->ip_addr_type == IP_NONE_ADDR_EXTRACT)
-			flow->qos_rule_size = offset + size;
+		if (key_profile->ip_addr_type == IP_NONE_ADDR_EXTRACT) {
+			if (offset >= flow->qos_rule_size) {
+				flow->qos_rule_size = offset + size;
+			} else if ((offset + size) > flow->qos_rule_size) {
+				DPAA2_PMD_ERR("%s: %s < %s, but %s + %s > %s",
+					__func__, offset_info, rule_size_info,
+					offset_info, size_info, rule_size_info);
+				return -EINVAL;
+			}
+		}
 	}
 
 	if (dist_type & DPAA2_FLOW_FS_TYPE) {
+		sprintf(rule_size_info, "fs rule size(%d)",
+			flow->fs_rule_size);
 		memcpy((flow->fs_key_addr + offset), key, size);
 		memcpy((flow->fs_mask_addr + offset), mask, size);
-		if (key_profile->ip_addr_type == IP_NONE_ADDR_EXTRACT)
-			flow->fs_rule_size = offset + size;
+		if (key_profile->ip_addr_type == IP_NONE_ADDR_EXTRACT) {
+			if (offset >= flow->fs_rule_size) {
+				flow->fs_rule_size = offset + size;
+			} else if ((offset + size) > flow->fs_rule_size) {
+				DPAA2_PMD_ERR("%s: %s < %s, but %s + %s > %s",
+					__func__, offset_info, rule_size_info,
+					offset_info, size_info, rule_size_info);
+				return -EINVAL;
+			}
+		}
 	}
 
 	return 0;
@@ -1602,6 +1652,7 @@ dpaa2_flow_raw_rule_data_set(struct dpaa2_dev_flow *flow,
 	int extract_size = size > DPAA2_FLOW_MAX_KEY_SIZE ?
 		DPAA2_FLOW_MAX_KEY_SIZE : size;
 	int offset, field;
+	char offset_info[64], size_info[64], rule_size_info[64];
 
 	field = extract_offset << DPAA2_FLOW_RAW_OFFSET_FIELD_SHIFT;
 	field |= extract_size;
@@ -1612,17 +1663,37 @@ dpaa2_flow_raw_rule_data_set(struct dpaa2_dev_flow *flow,
 			extract_offset, size);
 		return -EINVAL;
 	}
+	sprintf(offset_info, "offset(%d)", offset);
+	sprintf(size_info, "size(%d)", size);
 
 	if (dist_type & DPAA2_FLOW_QOS_TYPE) {
+		sprintf(rule_size_info, "qos rule size(%d)",
+			flow->qos_rule_size);
 		memcpy((flow->qos_key_addr + offset), key, size);
 		memcpy((flow->qos_mask_addr + offset), mask, size);
-		flow->qos_rule_size = offset + size;
+		if (offset >= flow->qos_rule_size) {
+			flow->qos_rule_size = offset + size;
+		} else if ((offset + size) > flow->qos_rule_size) {
+			DPAA2_PMD_ERR("%s: %s < %s, but %s + %s > %s",
+				__func__, offset_info, rule_size_info,
+				offset_info, size_info, rule_size_info);
+			return -EINVAL;
+		}
 	}
 
 	if (dist_type & DPAA2_FLOW_FS_TYPE) {
+		sprintf(rule_size_info, "fs rule size(%d)",
+			flow->fs_rule_size);
 		memcpy((flow->fs_key_addr + offset), key, size);
 		memcpy((flow->fs_mask_addr + offset), mask, size);
-		flow->fs_rule_size = offset + size;
+		if (offset >= flow->fs_rule_size) {
+			flow->fs_rule_size = offset + size;
+		} else if ((offset + size) > flow->fs_rule_size) {
+			DPAA2_PMD_ERR("%s: %s < %s, but %s + %s > %s",
+				__func__, offset_info, rule_size_info,
+				offset_info, size_info, rule_size_info);
+			return -EINVAL;
+		}
 	}
 
 	return 0;
-- 
2.43.0

[PATCH 07/15] net/dpaa2: add dpmac MC header file

[Prashant Gupta]

This patch upgrades the MC firmware release API compatibility
to 10.39.0. Added mc/fsl_dpmac.h file.

Signed-off-by: Prashant Gupta <prashant.gupta_3@nxp.com>
---
 drivers/net/dpaa2/mc/fsl_dpmac.h | 465 +++++++++++++++++++++++++++++++
 1 file changed, 465 insertions(+)
 create mode 100644 drivers/net/dpaa2/mc/fsl_dpmac.h

diff --git a/drivers/net/dpaa2/mc/fsl_dpmac.h b/drivers/net/dpaa2/mc/fsl_dpmac.h
new file mode 100644
index 0000000000..41eca47cfa
--- /dev/null
+++ b/drivers/net/dpaa2/mc/fsl_dpmac.h
@@ -0,0 +1,465 @@
+/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
+ *
+ * Copyright 2013-2016 Freescale Semiconductor Inc.
+ * Copyright 2018-2025 NXP
+ *
+ */
+
+#ifndef __FSL_DPMAC_H
+#define __FSL_DPMAC_H
+
+/** @addtogroup dpmac Data Path MAC API
+ * Contains initialization APIs and runtime control APIs for DPMAC
+ * @{
+ */
+
+struct fsl_mc_io;
+
+int dpmac_open(struct fsl_mc_io *mc_io,
+	       uint32_t cmd_flags,
+	       int dpmac_id,
+	       uint16_t *token);
+
+int dpmac_close(struct fsl_mc_io *mc_io,
+		uint32_t cmd_flags,
+		uint16_t token);
+
+/**
+ * enum dpmac_link_type -  DPMAC link type
+ * @DPMAC_LINK_TYPE_NONE: No link
+ * @DPMAC_LINK_TYPE_FIXED: Link is fixed type
+ * @DPMAC_LINK_TYPE_PHY: Link by PHY ID
+ * @DPMAC_LINK_TYPE_BACKPLANE: Backplane link type
+ */
+enum dpmac_link_type {
+	DPMAC_LINK_TYPE_NONE,
+	DPMAC_LINK_TYPE_FIXED,
+	DPMAC_LINK_TYPE_PHY,
+	DPMAC_LINK_TYPE_BACKPLANE
+};
+
+/**
+ * enum dpmac_eth_if - DPMAC Ethrnet interface
+ * @DPMAC_ETH_IF_MII: MII interface
+ * @DPMAC_ETH_IF_RMII: RMII interface
+ * @DPMAC_ETH_IF_SMII: SMII interface
+ * @DPMAC_ETH_IF_GMII: GMII interface
+ * @DPMAC_ETH_IF_RGMII: RGMII interface
+ * @DPMAC_ETH_IF_SGMII: SGMII interface
+ * @DPMAC_ETH_IF_QSGMII: QSGMII interface
+ * @DPMAC_ETH_IF_XAUI: XAUI interface
+ * @DPMAC_ETH_IF_XFI: XFI interface
+ * @DPMAC_ETH_IF_CAUI: CAUI interface
+ * @DPMAC_ETH_IF_1000BASEX: 1000BASEX interface
+ * @DPMAC_ETH_IF_USXGMII: USXGMII interface
+ */
+enum dpmac_eth_if {
+	DPMAC_ETH_IF_MII,
+	DPMAC_ETH_IF_RMII,
+	DPMAC_ETH_IF_SMII,
+	DPMAC_ETH_IF_GMII,
+	DPMAC_ETH_IF_RGMII,
+	DPMAC_ETH_IF_SGMII,
+	DPMAC_ETH_IF_QSGMII,
+	DPMAC_ETH_IF_XAUI,
+	DPMAC_ETH_IF_XFI,
+	DPMAC_ETH_IF_CAUI,
+	DPMAC_ETH_IF_1000BASEX,
+	DPMAC_ETH_IF_USXGMII,
+};
+/*
+ * @DPMAC_FEC_NONE: RS-FEC (enabled by default) is disabled
+ * @DPMAC_FEC_RS: RS-FEC (Clause 91) mode configured
+ * @DPMAC_FEC_FC: FC-FEC (Clause 74) mode configured (not yet supported)
+ */
+enum dpmac_fec_mode {
+	DPMAC_FEC_NONE,
+	DPMAC_FEC_RS,
+	DPMAC_FEC_FC,
+};
+
+/* serdes sfi/custom settings feature internals
+ * @SERDES_CFG_DEFAULT: the default configuration.
+ * @SERDES_CFG_SFI: default operating mode for XFI interfaces
+ * @SERDES_CFG_CUSTOM: It allows the user to manually configure the type of equalization,
+ *	amplitude, preq and post1q settings. Can be used with all interfaces except RGMII.
+ */
+enum serdes_eq_cfg_mode {
+	SERDES_CFG_DEFAULT = 0,
+	SERDES_CFG_SFI,
+	SERDES_CFG_CUSTOM,
+};
+
+/**
+ * struct dpmac_cfg - Structure representing DPMAC configuration
+ * @mac_id:	Represents the Hardware MAC ID; in case of multiple WRIOP,
+ *		the MAC IDs are continuous.
+ *		For example:  2 WRIOPs, 16 MACs in each:
+ *				MAC IDs for the 1st WRIOP: 1-16,
+ *				MAC IDs for the 2nd WRIOP: 17-32.
+ */
+struct dpmac_cfg {
+	uint16_t mac_id;
+};
+
+int dpmac_create(struct fsl_mc_io *mc_io,
+		 uint16_t dprc_token,
+		 uint32_t cmd_flags,
+		 const struct dpmac_cfg *cfg,
+		 uint32_t *obj_id);
+
+int dpmac_destroy(struct fsl_mc_io *mc_io,
+		  uint16_t dprc_token,
+		  uint32_t cmd_flags,
+		  uint32_t object_id);
+
+/**
+ * DPMAC IRQ Index and Events
+ */
+
+/**
+ * IRQ index
+ */
+#define DPMAC_IRQ_INDEX				0
+/**
+ * IRQ event - indicates a change in link state
+ */
+#define DPMAC_IRQ_EVENT_LINK_CFG_REQ		0x00000001
+/**
+ * IRQ event - Indicates that the link state changed
+ */
+#define DPMAC_IRQ_EVENT_LINK_CHANGED		0x00000002
+/**
+ * IRQ event - The object requests link up
+ */
+#define DPMAC_IRQ_EVENT_LINK_UP_REQ			0x00000004
+/**
+ * IRQ event - The object requests link down
+ */
+#define DPMAC_IRQ_EVENT_LINK_DOWN_REQ		0x00000008
+/**
+ * IRQ event - indicates a change in endpoint
+ */
+#define DPMAC_IRQ_EVENT_ENDPOINT_CHANGED	0x00000010
+
+int dpmac_set_irq_enable(struct fsl_mc_io *mc_io,
+			 uint32_t cmd_flags,
+			 uint16_t token,
+			 uint8_t irq_index,
+			 uint8_t en);
+
+int dpmac_get_irq_enable(struct fsl_mc_io *mc_io,
+			 uint32_t cmd_flags,
+			 uint16_t token,
+			 uint8_t irq_index,
+			 uint8_t *en);
+
+int dpmac_set_irq_mask(struct fsl_mc_io *mc_io,
+		       uint32_t cmd_flags,
+		       uint16_t token,
+		       uint8_t irq_index,
+		       uint32_t mask);
+
+int dpmac_get_irq_mask(struct fsl_mc_io *mc_io,
+		       uint32_t cmd_flags,
+		       uint16_t token,
+		       uint8_t irq_index,
+		       uint32_t *mask);
+
+int dpmac_get_irq_status(struct fsl_mc_io *mc_io,
+			 uint32_t cmd_flags,
+			 uint16_t token,
+			 uint8_t irq_index,
+			 uint32_t *status);
+
+int dpmac_clear_irq_status(struct fsl_mc_io *mc_io,
+			   uint32_t cmd_flags,
+			   uint16_t token,
+			   uint8_t irq_index,
+			   uint32_t status);
+
+/**
+ * @brief	Inter-Frame Gap mode
+ *
+ * LAN/WAN uses different Inter-Frame Gap mode
+ */
+enum dpmac_ifg_mode {
+	DPMAC_IFG_MODE_FIXED,
+	/*!< IFG length represents number of octets in steps of 4 */
+	DPMAC_IFG_MODE_STRETCHED
+	/*!< IFG length represents the stretch factor */
+};
+
+/**
+ * @brief Structure representing Inter-Frame Gap mode configuration
+ */
+struct dpmac_ifg_cfg {
+	enum dpmac_ifg_mode ipg_mode; /*!< WAN/LAN mode */
+	uint8_t ipg_length; /*!< IPG Length, default value is 0xC */
+};
+
+/**
+ * @brief Structure used to read through MDIO
+ */
+struct dpmac_mdio_read {
+	uint8_t cl45; /*!< Clause 45 */
+	uint8_t phy_addr; /*!< MDIO PHY address */
+	uint16_t reg; /*!< PHY register */
+};
+
+/**
+ * @brief Structure used to write through MDIO
+ */
+struct dpmac_mdio_write {
+	uint8_t cl45; /*!< Clause 45 */
+	uint8_t phy_addr; /*!< MDIO PHY address */
+	uint16_t reg; /*!< PHY register */
+	uint16_t data; /*!< Data to be written */
+};
+
+#define DPMAC_SET_PARAMS_IFG 0x1
+
+/**
+ * struct serdes_eq_settings - Structure  SerDes equalization settings
+ * cfg: serdes sfi/custom/default settings feature internals
+ * @eq_type: Number of levels of TX equalization
+ * @sgn_preq: Precursor sign indicating direction of eye closure
+ * @eq_preq: Drive strength of TX full swing transition bit to precursor
+ * @sgn_post1q: First post-cursor sign indicating direction of eye closure
+ * @eq_post1q: Drive strength of full swing transition bit to first post-cursor
+ * @eq_amp_red: Overall transmit amplitude reduction
+ */
+struct serdes_eq_settings {
+	enum serdes_eq_cfg_mode cfg;
+	int eq_type;
+	int sgn_preq;
+	int eq_preq;
+	int sgn_post1q;
+	int eq_post1q;
+	int eq_amp_red;
+};
+
+/**
+ * struct dpmac_attr - Structure representing DPMAC attributes
+ * @id:		DPMAC object ID
+ * @max_rate:	Maximum supported rate - in Mbps
+ * @eth_if:	Ethernet interface
+ * @link_type:	link type
+ * @fec_mode:	FEC mode - Configurable only for 25G interfaces
+ * serdes_cfg:	SerDes equalization settings
+ */
+struct dpmac_attr {
+	uint16_t id;
+	uint32_t max_rate;
+	enum dpmac_eth_if eth_if;
+	enum dpmac_link_type link_type;
+	enum dpmac_fec_mode fec_mode;
+	struct serdes_eq_settings serdes_cfg;
+	struct dpmac_ifg_cfg ifg_cfg;
+};
+
+int dpmac_get_attributes(struct fsl_mc_io *mc_io,
+			 uint32_t cmd_flags,
+			 uint16_t token,
+			 struct dpmac_attr *attr);
+
+int dpmac_set_params(struct fsl_mc_io *mc_io,
+		       uint32_t cmd_flags,
+		       uint16_t token,
+			   uint32_t flags,
+			   struct dpmac_ifg_cfg ifg_cfg);
+
+int dpmac_get_mac_addr(struct fsl_mc_io *mc_io,
+			   uint32_t cmd_flags,
+			   uint16_t token,
+			   uint8_t mac_addr[6]);
+
+/**
+ * DPMAC link configuration/state options
+ */
+
+/**
+ * Enable auto-negotiation
+ */
+#define DPMAC_LINK_OPT_AUTONEG		0x0000000000000001ULL
+/**
+ * Enable half-duplex mode
+ */
+#define DPMAC_LINK_OPT_HALF_DUPLEX	0x0000000000000002ULL
+/**
+ * Enable pause frames
+ */
+#define DPMAC_LINK_OPT_PAUSE		0x0000000000000004ULL
+/**
+ * Enable a-symmetric pause frames
+ */
+#define DPMAC_LINK_OPT_ASYM_PAUSE	0x0000000000000008ULL
+/**
+ * Advertise 10MB full duplex
+ */
+#define DPMAC_ADVERTISED_10BASET_FULL           0x0000000000000001ULL
+/**
+ * Advertise 100MB full duplex
+ */
+#define DPMAC_ADVERTISED_100BASET_FULL          0x0000000000000002ULL
+/**
+ * Advertise 1GB full duplex
+ */
+#define DPMAC_ADVERTISED_1000BASET_FULL         0x0000000000000004ULL
+/**
+ * Advertise auto-negotiation enable
+ */
+#define DPMAC_ADVERTISED_AUTONEG                0x0000000000000008ULL
+/**
+ * Advertise 10GB full duplex
+ */
+#define DPMAC_ADVERTISED_10000BASET_FULL        0x0000000000000010ULL
+/**
+ * Advertise 2.5GB full duplex
+ */
+#define DPMAC_ADVERTISED_2500BASEX_FULL         0x0000000000000020ULL
+/**
+ * Advertise 5GB full duplex
+ */
+#define DPMAC_ADVERTISED_5000BASET_FULL         0x0000000000000040ULL
+
+/**
+ * struct dpmac_link_cfg - Structure representing DPMAC link configuration
+ * @rate: Link's rate - in Mbps
+ * @options: Enable/Disable DPMAC link cfg features (bitmap)
+ * @advertising: Speeds that are advertised for autoneg (bitmap)
+ */
+struct dpmac_link_cfg {
+	uint32_t rate;
+	uint64_t options;
+	uint64_t advertising;
+};
+
+int dpmac_get_link_cfg(struct fsl_mc_io *mc_io,
+		       uint32_t cmd_flags,
+		       uint16_t token,
+		       struct dpmac_link_cfg *cfg);
+
+/**
+ * struct dpmac_link_state - DPMAC link configuration request
+ * @rate: Rate in Mbps
+ * @options: Enable/Disable DPMAC link cfg features (bitmap)
+ * @up: Link state
+ * @state_valid: Ignore/Update the state of the link
+ * @supported: Speeds capability of the phy (bitmap)
+ * @advertising: Speeds that are advertised for autoneg (bitmap)
+ */
+struct dpmac_link_state {
+	uint32_t rate;
+	uint64_t options;
+	int up;
+	int state_valid;
+	uint64_t supported;
+	uint64_t advertising;
+};
+
+int dpmac_set_link_state(struct fsl_mc_io *mc_io,
+			 uint32_t cmd_flags,
+			 uint16_t token,
+			 struct dpmac_link_state *link_state);
+
+/**
+ * enum dpmac_counter - DPMAC counter types
+ * @DPMAC_CNT_ING_FRAME_64: counts 64-bytes frames, good or bad.
+ * @DPMAC_CNT_ING_FRAME_127: counts 65- to 127-bytes frames, good or bad.
+ * @DPMAC_CNT_ING_FRAME_255: counts 128- to 255-bytes frames, good or bad.
+ * @DPMAC_CNT_ING_FRAME_511: counts 256- to 511-bytes frames, good or bad.
+ * @DPMAC_CNT_ING_FRAME_1023: counts 512- to 1023-bytes frames, good or bad.
+ * @DPMAC_CNT_ING_FRAME_1518: counts 1024- to 1518-bytes frames, good or bad.
+ * @DPMAC_CNT_ING_FRAME_1519_MAX: counts 1519-bytes frames and larger
+ *				  (up to max frame length specified),
+ *				  good or bad.
+ * @DPMAC_CNT_ING_FRAG: counts frames which are shorter than 64 bytes received
+ *			with a wrong CRC
+ * @DPMAC_CNT_ING_JABBER: counts frames longer than the maximum frame length
+ *			  specified, with a bad frame check sequence.
+ * @DPMAC_CNT_ING_FRAME_DISCARD: counts dropped frames due to internal errors.
+ *				 Occurs when a receive FIFO overflows.
+ *				 Includes also frames truncated as a result of
+ *				 the receive FIFO overflow.
+ * @DPMAC_CNT_ING_ALIGN_ERR: counts frames with an alignment error
+ *			     (optional used for wrong SFD).
+ * @DPMAC_CNT_EGR_UNDERSIZED: counts frames transmitted that was less than 64
+ *			      bytes long with a good CRC.
+ * @DPMAC_CNT_ING_OVERSIZED: counts frames longer than the maximum frame length
+ *			     specified, with a good frame check sequence.
+ * @DPMAC_CNT_ING_VALID_PAUSE_FRAME: counts valid pause frames (regular and PFC)
+ * @DPMAC_CNT_EGR_VALID_PAUSE_FRAME: counts valid pause frames transmitted
+ *				     (regular and PFC).
+ * @DPMAC_CNT_ING_BYTE: counts bytes received except preamble for all valid
+ *			frames and valid pause frames.
+ * @DPMAC_CNT_ING_MCAST_FRAME: counts received multicast frames.
+ * @DPMAC_CNT_ING_BCAST_FRAME: counts received broadcast frames.
+ * @DPMAC_CNT_ING_ALL_FRAME: counts each good or bad frames received.
+ * @DPMAC_CNT_ING_UCAST_FRAME: counts received unicast frames.
+ * @DPMAC_CNT_ING_ERR_FRAME: counts frames received with an error
+ *			     (except for undersized/fragment frame).
+ * @DPMAC_CNT_EGR_BYTE: counts bytes transmitted except preamble for all valid
+ *			frames and valid pause frames transmitted.
+ * @DPMAC_CNT_EGR_MCAST_FRAME: counts transmitted multicast frames.
+ * @DPMAC_CNT_EGR_BCAST_FRAME: counts transmitted broadcast frames.
+ * @DPMAC_CNT_EGR_UCAST_FRAME: counts transmitted unicast frames.
+ * @DPMAC_CNT_EGR_ERR_FRAME: counts frames transmitted with an error.
+ * @DPMAC_CNT_ING_GOOD_FRAME: counts frames received without error, including
+ *			      pause frames.
+ * @DPMAC_CNT_EGR_GOOD_FRAME: counts frames transmitted without error, including
+ *			      pause frames.
+ */
+enum dpmac_counter {
+	DPMAC_CNT_ING_FRAME_64,
+	DPMAC_CNT_ING_FRAME_127,
+	DPMAC_CNT_ING_FRAME_255,
+	DPMAC_CNT_ING_FRAME_511,
+	DPMAC_CNT_ING_FRAME_1023,
+	DPMAC_CNT_ING_FRAME_1518,
+	DPMAC_CNT_ING_FRAME_1519_MAX,
+	DPMAC_CNT_ING_FRAG,
+	DPMAC_CNT_ING_JABBER,
+	DPMAC_CNT_ING_FRAME_DISCARD,
+	DPMAC_CNT_ING_ALIGN_ERR,
+	DPMAC_CNT_EGR_UNDERSIZED,
+	DPMAC_CNT_ING_OVERSIZED,
+	DPMAC_CNT_ING_VALID_PAUSE_FRAME,
+	DPMAC_CNT_EGR_VALID_PAUSE_FRAME,
+	DPMAC_CNT_ING_BYTE,
+	DPMAC_CNT_ING_MCAST_FRAME,
+	DPMAC_CNT_ING_BCAST_FRAME,
+	DPMAC_CNT_ING_ALL_FRAME,
+	DPMAC_CNT_ING_UCAST_FRAME,
+	DPMAC_CNT_ING_ERR_FRAME,
+	DPMAC_CNT_EGR_BYTE,
+	DPMAC_CNT_EGR_MCAST_FRAME,
+	DPMAC_CNT_EGR_BCAST_FRAME,
+	DPMAC_CNT_EGR_UCAST_FRAME,
+	DPMAC_CNT_EGR_ERR_FRAME,
+	DPMAC_CNT_ING_GOOD_FRAME,
+	DPMAC_CNT_EGR_GOOD_FRAME
+};
+
+int dpmac_get_counter(struct fsl_mc_io *mc_io,
+		      uint32_t cmd_flags,
+		      uint16_t token,
+		      enum dpmac_counter  type,
+		      uint64_t *counter);
+
+int dpmac_get_api_version(struct fsl_mc_io *mc_io,
+			  uint32_t cmd_flags,
+			  uint16_t *major_ver,
+			  uint16_t *minor_ver);
+
+int dpmac_reset(struct fsl_mc_io *mc_io,
+		uint32_t cmd_flags,
+		uint16_t token);
+
+int dpmac_set_protocol(struct fsl_mc_io *mc_io, uint32_t cmd_flags,
+		       uint16_t token, enum dpmac_eth_if protocol);
+
+int dpmac_get_statistics(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token,
+			 uint64_t iova_cnt, uint64_t iova_values, uint32_t num_cnt);
+
+#endif /* __FSL_DPMAC_H */
-- 
2.43.0

[PATCH 08/15] net/dpaa2: support dpmac counters in stats

[Prashant Gupta]

From: Vanshika Shukla <vanshika.shukla@nxp.com>

Add support of dpmac counters in xstats.

Signed-off-by: Vanshika Shukla <vanshika.shukla@nxp.com>
---
 doc/guides/rel_notes/release_25_11.rst |   3 +
 drivers/net/dpaa2/dpaa2_ethdev.c       | 138 +++++++++++++++++++++++--
 drivers/net/dpaa2/dpaa2_ethdev.h       |  14 ++-
 drivers/net/dpaa2/mc/dpni.c            |  29 +++++-
 drivers/net/dpaa2/mc/fsl_dpmac.h       |  48 ++++++++-
 drivers/net/dpaa2/mc/fsl_dpni.h        |   3 +
 drivers/net/dpaa2/mc/fsl_dpni_cmd.h    |  11 +-
 7 files changed, 233 insertions(+), 13 deletions(-)

diff --git a/doc/guides/rel_notes/release_25_11.rst b/doc/guides/rel_notes/release_25_11.rst
index c3b94e1896..ba73d7deb8 100644
--- a/doc/guides/rel_notes/release_25_11.rst
+++ b/doc/guides/rel_notes/release_25_11.rst
@@ -76,6 +76,9 @@ New Features
   * Added multi-process per port.
   * Optimized code.
 
+* **Updated DPAA2 ethernet driver.**
+
+  * Added additional MAC counters in xstats.
 
 Removed Items
 -------------
diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c
index 0fd577c448..5c4c0ae462 100644
--- a/drivers/net/dpaa2/dpaa2_ethdev.c
+++ b/drivers/net/dpaa2/dpaa2_ethdev.c
@@ -1,7 +1,7 @@
 /* * SPDX-License-Identifier: BSD-3-Clause
  *
  *   Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
- *   Copyright 2016-2024 NXP
+ *   Copyright 2016-2025 NXP
  *
  */
 
@@ -106,6 +106,52 @@ static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = {
 	{"egress_confirmed_frames", 2, 4},
 	{"cgr_reject_frames", 4, 0},
 	{"cgr_reject_bytes", 4, 1},
+	{"mac_rx_64 bytes", 0, 0},
+	{"mac_rx_65-127 bytes", 0, 0},
+	{"mac_rx_128-255 bytes", 0, 0},
+	{"mac_rx_256-511 bytes", 0, 0},
+	{"mac_rx_512-1023 bytes", 0, 0},
+	{"mac_rx_1024-1518 bytes", 0, 0},
+	{"mac_rx_1519-max bytes", 0, 0},
+	{"mac_rx_frags", 0, 0},
+	{"mac_rx_jabber", 0, 0},
+	{"mac_rx_frame discards", 0, 0},
+	{"mac_rx_align errors", 0, 0},
+	{"mac_tx_undersized", 0, 0},
+	{"mac_rx_oversized", 0, 0},
+	{"mac_rx_pause", 0, 0},
+	{"mac_tx_b-pause", 0, 0},
+	{"mac_rx_bytes", 0, 0},
+	{"mac_rx_m-cast", 0, 0},
+	{"mac_rx_b-cast", 0, 0},
+	{"mac_rx_all frames", 0, 0},
+	{"mac_rx_u-cast", 0, 0},
+	{"mac_rx_frame errors", 0, 0},
+	{"mac_tx_bytes", 0, 0},
+	{"mac_tx_m-cast", 0, 0},
+	{"mac_tx_b-cast", 0, 0},
+	{"mac_tx_u-cast", 0, 0},
+	{"mac_tx_frame errors", 0, 0},
+	{"mac_rx_frames ok", 0, 0},
+	{"mac_tx_frames ok", 0, 0},
+	{"mac_tx_64 bytes", 0, 0},
+	{"mac_tx_65-127 bytes", 0, 0},
+	{"mac_tx_128-255 bytes", 0, 0},
+	{"mac_tx_256-511 bytes", 0, 0},
+	{"mac_tx_512-1023 bytes", 0, 0},
+	{"mac_tx_1024-1518 bytes", 0, 0},
+	{"mac_tx_1519-max bytes", 0, 0},
+	{"mac_rx_all_bytes", 0, 0},
+	{"mac_rx_fcs_err", 0, 0},
+	{"mac_rx_vlan_frame", 0, 0},
+	{"mac_rx_undersized", 0, 0},
+	{"mac_rx_control_frame", 0, 0},
+	{"mac_rx_frame_discard_not_trunc", 0, 0},
+	{"mac_tx_all_bytes", 0, 0},
+	{"mac_tx_fcs_err", 0, 0},
+	{"mac_tx_vlan_frame", 0, 0},
+	{"mac_tx_all_frame", 0, 0},
+	{"mac_tx_control_frame", 0, 0},
 };
 
 static struct rte_dpaa2_driver rte_dpaa2_pmd;
@@ -1680,16 +1726,67 @@ dpaa2_dev_stats_get(struct rte_eth_dev *dev,
 	return retcode;
 };
 
+void
+dpaa2_dev_mac_setup_stats(struct rte_eth_dev *dev)
+{
+	struct dpaa2_dev_priv *priv = dev->data->dev_private;
+	uint32_t *cnt_idx;
+	int i;
+
+	priv->cnt_idx_dma_mem = rte_malloc(NULL, DPAA2_MAC_STATS_INDEX_DMA_SIZE,
+					   RTE_CACHE_LINE_SIZE);
+	if (!priv->cnt_idx_dma_mem) {
+		DPAA2_PMD_ERR("Failure to allocate memory for mac index");
+		goto out;
+	}
+
+	priv->cnt_values_dma_mem = rte_malloc(NULL, DPAA2_MAC_STATS_VALUE_DMA_SIZE,
+					      RTE_CACHE_LINE_SIZE);
+	if (!priv->cnt_values_dma_mem) {
+		DPAA2_PMD_ERR("Failure to allocate memory for mac values");
+		goto err_alloc_values;
+	}
+
+	cnt_idx = priv->cnt_idx_dma_mem;
+	for (i = 0; i < DPAA2_MAC_NUM_STATS; i++)
+		*cnt_idx++ = rte_cpu_to_le_32((uint32_t)i);
+
+	priv->cnt_idx_iova = rte_mem_virt2iova(priv->cnt_idx_dma_mem);
+	if (priv->cnt_idx_iova == RTE_BAD_IOVA) {
+		DPAA2_PMD_ERR("%s: No IOMMU map for count index dma mem(%p)",
+			__func__, priv->cnt_idx_dma_mem);
+		goto err_dma_map;
+	}
+
+	priv->cnt_values_iova = rte_mem_virt2iova(priv->cnt_values_dma_mem);
+	if (priv->cnt_values_iova == RTE_BAD_IOVA) {
+		DPAA2_PMD_ERR("%s: No IOMMU map for count values dma mem(%p)",
+			__func__, priv->cnt_values_dma_mem);
+		goto err_dma_map;
+	}
+
+	return;
+
+err_dma_map:
+	rte_free(priv->cnt_values_dma_mem);
+err_alloc_values:
+	rte_free(priv->cnt_idx_dma_mem);
+out:
+	priv->cnt_idx_dma_mem = NULL;
+	priv->cnt_values_dma_mem = NULL;
+}
+
 static int
 dpaa2_dev_xstats_get(struct rte_eth_dev *dev,
 	struct rte_eth_xstat *xstats, unsigned int n)
 {
-	struct dpaa2_dev_priv *priv = dev->data->dev_private;
 	struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
-	int32_t retcode;
+	unsigned int i = 0, j = 0, num = RTE_DIM(dpaa2_xstats_strings);
+	struct dpaa2_dev_priv *priv = dev->data->dev_private;
 	union dpni_statistics value[5] = {};
-	unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings);
 	uint8_t page_id, stats_id;
+	uint64_t *cnt_values;
+	int32_t retcode;
 
 	if (n < num)
 		return num;
@@ -1715,8 +1812,8 @@ dpaa2_dev_xstats_get(struct rte_eth_dev *dev,
 	if (retcode)
 		goto err;
 
-	for (i = 0; i < priv->max_cgs; i++) {
-		if (!priv->cgid_in_use[i]) {
+	for (j = 0; j < priv->max_cgs; j++) {
+		if (!priv->cgid_in_use[j]) {
 			/* Get Counters from page_4*/
 			retcode = dpni_get_statistics(dpni, CMD_PRI_LOW,
 						      priv->token,
@@ -1726,13 +1823,38 @@ dpaa2_dev_xstats_get(struct rte_eth_dev *dev,
 			break;
 		}
 	}
-
-	for (i = 0; i < num; i++) {
+	while (i < (num - DPAA2_MAC_NUM_STATS)) {
 		xstats[i].id = i;
 		page_id = dpaa2_xstats_strings[i].page_id;
 		stats_id = dpaa2_xstats_strings[i].stats_id;
 		xstats[i].value = value[page_id].raw.counter[stats_id];
+		i++;
+	}
+
+	dpaa2_dev_mac_setup_stats(dev);
+	retcode = dpni_get_mac_statistics(dpni, CMD_PRI_LOW, priv->token,
+					  priv->cnt_idx_iova, priv->cnt_values_iova,
+					  DPAA2_MAC_NUM_STATS);
+	if (retcode) {
+		DPAA2_PMD_WARN("MAC (mac_*) counters are not supported!!");
+		rte_free(priv->cnt_values_dma_mem);
+		rte_free(priv->cnt_idx_dma_mem);
+		while (i >= (num - DPAA2_MAC_NUM_STATS) && i < num) {
+			xstats[i].id = i;
+			xstats[i].value = 0;
+			i++;
+		}
 	}
+	if (!retcode) {
+		cnt_values = priv->cnt_values_dma_mem;
+		while (i >= (num - DPAA2_MAC_NUM_STATS) && i < num) {
+			/* mac counters value */
+			xstats[i].id = i;
+			xstats[i].value = rte_le_to_cpu_64(*cnt_values++);
+			i++;
+		}
+	}
+
 	return i;
 err:
 	DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode);
diff --git a/drivers/net/dpaa2/dpaa2_ethdev.h b/drivers/net/dpaa2/dpaa2_ethdev.h
index ffc9ebadb8..6026b378a7 100644
--- a/drivers/net/dpaa2/dpaa2_ethdev.h
+++ b/drivers/net/dpaa2/dpaa2_ethdev.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  *
  *   Copyright (c) 2015-2016 Freescale Semiconductor, Inc. All rights reserved.
- *   Copyright 2016-2022 NXP
+ *   Copyright 2016-2025 NXP
  *
  */
 
@@ -18,6 +18,7 @@
 
 #include <mc/fsl_dpni.h>
 #include <mc/fsl_mc_sys.h>
+#include <mc/fsl_dpmac.h>
 
 #include "base/dpaa2_hw_dpni_annot.h"
 
@@ -133,6 +134,11 @@
 #define DPAA2_PKT_TYPE_VLAN_1		0x0160
 #define DPAA2_PKT_TYPE_VLAN_2		0x0260
 
+/* mac counters */
+#define DPAA2_MAC_NUM_STATS            (DPMAC_CNT_EGR_CONTROL_FRAME + 1)
+#define DPAA2_MAC_STATS_INDEX_DMA_SIZE (DPAA2_MAC_NUM_STATS * sizeof(uint32_t))
+#define DPAA2_MAC_STATS_VALUE_DMA_SIZE (DPAA2_MAC_NUM_STATS * sizeof(uint64_t))
+
 /* Global pool used by driver for SG list TX */
 extern struct rte_mempool *dpaa2_tx_sg_pool;
 /* Maximum SG segments */
@@ -419,6 +425,10 @@ struct dpaa2_dev_priv {
 	uint8_t channel_inuse;
 	/* Stores correction offset for one step timestamping */
 	uint16_t ptp_correction_offset;
+	/* for mac counters */
+	uint32_t *cnt_idx_dma_mem;
+	uint64_t *cnt_values_dma_mem;
+	uint64_t cnt_idx_iova, cnt_values_iova;
 
 	struct dpaa2_dev_flow *curr;
 	LIST_HEAD(, dpaa2_dev_flow) flows;
@@ -504,4 +514,6 @@ int dpaa2_dev_recycle_qp_setup(struct rte_dpaa2_device *dpaa2_dev,
 	struct dpaa2_queue **txq,
 	struct dpaa2_queue **rxq);
 
+void
+dpaa2_dev_mac_setup_stats(struct rte_eth_dev *dev);
 #endif /* _DPAA2_ETHDEV_H */
diff --git a/drivers/net/dpaa2/mc/dpni.c b/drivers/net/dpaa2/mc/dpni.c
index 558f08dc69..f651f29b02 100644
--- a/drivers/net/dpaa2/mc/dpni.c
+++ b/drivers/net/dpaa2/mc/dpni.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
  *
  * Copyright 2013-2016 Freescale Semiconductor Inc.
- * Copyright 2016-2023 NXP
+ * Copyright 2016-2025 NXP
  *
  */
 #include <fsl_mc_sys.h>
@@ -3493,3 +3493,30 @@ int dpni_sp_enable(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token,
 	/* send command to MC */
 	return mc_send_command(mc_io, &cmd);
 }
+/**
+ * dpni_get_mac_statistics() - Get statistics on the connected DPMAC objects
+ * @mc_io:       Pointer to opaque I/O object
+ * @cmd_flags:   Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:       Token of DPMAC object
+ * @iova_cnt:    IOVA containing the requested MAC counters formatted as an
+ *               array of __le32 representing the dpmac_counter_id.
+ * @iova_values: IOVA containing the values for all the requested counters
+ *               formatted as an array of __le64.
+ * @num_cnt:     Number of counters requested
+ *
+ * Return:       '0' on Success; Error code otherwise.
+ */
+int dpni_get_mac_statistics(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token,
+			    uint64_t iova_cnt, uint64_t iova_values, uint32_t num_cnt)
+{
+	struct dpni_cmd_get_mac_statistics *cmd_params;
+	struct mc_command cmd = { 0 };
+
+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_MAC_STATISTICS, cmd_flags, token);
+	cmd_params = (struct dpni_cmd_get_mac_statistics *)cmd.params;
+	cmd_params->iova_cnt = cpu_to_le64(iova_cnt);
+	cmd_params->iova_values = cpu_to_le64(iova_values);
+	cmd_params->num_cnt = cpu_to_le32(num_cnt);
+
+	return mc_send_command(mc_io, &cmd);
+}
diff --git a/drivers/net/dpaa2/mc/fsl_dpmac.h b/drivers/net/dpaa2/mc/fsl_dpmac.h
index 41eca47cfa..375d646cfc 100644
--- a/drivers/net/dpaa2/mc/fsl_dpmac.h
+++ b/drivers/net/dpaa2/mc/fsl_dpmac.h
@@ -409,6 +409,34 @@ int dpmac_set_link_state(struct fsl_mc_io *mc_io,
  *			      pause frames.
  * @DPMAC_CNT_EGR_GOOD_FRAME: counts frames transmitted without error, including
  *			      pause frames.
+ * @DPMAC_CNT_EGR_FRAME_64: counts transmitted 64-bytes frames, good or bad.
+ * @DPMAC_CNT_EGR_FRAME_127: counts transmitted 65 to 127-bytes frames, good or bad.
+ * @DPMAC_CNT_EGR_FRAME_255: counts transmitted 128 to 255-bytes frames, good or bad.
+ * @DPMAC_CNT_EGR_FRAME_511: counts transmitted 256 to 511-bytes frames, good or bad.
+ * @DPMAC_CNT_EGR_FRAME_1023: counts transmitted 512 to 1023-bytes frames, good or bad.
+ * @DPMAC_CNT_EGR_FRAME_1518: counts transmitted 1024 to 1518-bytes frames, good or bad.
+ * @DPMAC_CNT_EGR_FRAME_1519_MAX: counts transmitted 1519-bytes frames and
+ * larger (up to max frame length specified), good or bad.
+ * @DPMAC_CNT_ING_ALL_BYTE: counts bytes received in both good and bad packets
+ * @DPMAC_CNT_ING_FCS_ERR: counts frames received with a CRC-32 error but the
+ * frame is otherwise of correct length
+ * @DPMAC_CNT_ING_VLAN_FRAME: counts the received VLAN tagged frames which are valid.
+ * @DPMAC_CNT_ING_UNDERSIZED: counts received frames which were less than 64
+ * bytes long and with a good CRC.
+ * @DPMAC_CNT_ING_CONTROL_FRAME: counts received control frames (type 0x8808)
+ * but not pause frames.
+ * @DPMAC_CNT_ING_FRAME_DISCARD_NOT_TRUNC: counts the fully dropped frames (not
+ * truncated) due to internal errors of the MAC client. Occurs when a received
+ * FIFO overflows.
+ * @DPMAC_CNT_EGR_ALL_BYTE: counts transmitted bytes in both good and bad
+ * packets.
+ * @DPMAC_CNT_EGR_FCS_ERR: counts transmitted frames with a CRC-32 error except
+ * for underflows.
+ * @DPMAC_CNT_EGR_VLAN_FRAME: counts the transmitted VLAN tagged frames which
+ * are valid.
+ * @DPMAC_CNT_EGR_ALL_FRAME: counts all transmitted frames, good or bad.
+ * @DPMAC_CNT_EGR_CONTROL_FRAME: counts transmitted control frames (type
+ * 0x8808) but not pause frames.
  */
 enum dpmac_counter {
 	DPMAC_CNT_ING_FRAME_64,
@@ -438,7 +466,25 @@ enum dpmac_counter {
 	DPMAC_CNT_EGR_UCAST_FRAME,
 	DPMAC_CNT_EGR_ERR_FRAME,
 	DPMAC_CNT_ING_GOOD_FRAME,
-	DPMAC_CNT_EGR_GOOD_FRAME
+	DPMAC_CNT_EGR_GOOD_FRAME,
+	DPMAC_CNT_EGR_FRAME_64,
+	DPMAC_CNT_EGR_FRAME_127,
+	DPMAC_CNT_EGR_FRAME_255,
+	DPMAC_CNT_EGR_FRAME_511,
+	DPMAC_CNT_EGR_FRAME_1023,
+	DPMAC_CNT_EGR_FRAME_1518,
+	DPMAC_CNT_EGR_FRAME_1519_MAX,
+	DPMAC_CNT_ING_ALL_BYTE,
+	DPMAC_CNT_ING_FCS_ERR,
+	DPMAC_CNT_ING_VLAN_FRAME,
+	DPMAC_CNT_ING_UNDERSIZED,
+	DPMAC_CNT_ING_CONTROL_FRAME,
+	DPMAC_CNT_ING_FRAME_DISCARD_NOT_TRUNC,
+	DPMAC_CNT_EGR_ALL_BYTE,
+	DPMAC_CNT_EGR_FCS_ERR,
+	DPMAC_CNT_EGR_VLAN_FRAME,
+	DPMAC_CNT_EGR_ALL_FRAME,
+	DPMAC_CNT_EGR_CONTROL_FRAME
 };
 
 int dpmac_get_counter(struct fsl_mc_io *mc_io,
diff --git a/drivers/net/dpaa2/mc/fsl_dpni.h b/drivers/net/dpaa2/mc/fsl_dpni.h
index 3a5fcfa8a5..2f8125314c 100644
--- a/drivers/net/dpaa2/mc/fsl_dpni.h
+++ b/drivers/net/dpaa2/mc/fsl_dpni.h
@@ -2014,4 +2014,7 @@ int dpni_set_sp_profile(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t to
 int dpni_sp_enable(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token,
 		uint8_t type, uint8_t en);
 
+int dpni_get_mac_statistics(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token,
+			    uint64_t iova_cnt, uint64_t iova_values, uint32_t num_cnt);
+
 #endif /* __FSL_DPNI_H */
diff --git a/drivers/net/dpaa2/mc/fsl_dpni_cmd.h b/drivers/net/dpaa2/mc/fsl_dpni_cmd.h
index 1152182e34..f653f2c0e4 100644
--- a/drivers/net/dpaa2/mc/fsl_dpni_cmd.h
+++ b/drivers/net/dpaa2/mc/fsl_dpni_cmd.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
  *
  * Copyright 2013-2016 Freescale Semiconductor Inc.
- * Copyright 2016-2023 NXP
+ * Copyright 2016-2025 NXP
  *
  */
 #ifndef _FSL_DPNI_CMD_H
@@ -9,7 +9,7 @@
 
 /* DPNI Version */
 #define DPNI_VER_MAJOR				8
-#define DPNI_VER_MINOR				4
+#define DPNI_VER_MINOR				6
 
 #define DPNI_CMD_BASE_VERSION			1
 #define DPNI_CMD_VERSION_2			2
@@ -131,6 +131,7 @@
 #define DPNI_CMDID_SP_ENABLE		    DPNI_CMD(0x280)
 #define DPNI_CMDID_SET_QUEUE_TX_CONFIRMATION_MODE	DPNI_CMD(0x281)
 #define DPNI_CMDID_GET_QUEUE_TX_CONFIRMATION_MODE	DPNI_CMD(0x282)
+#define DPNI_CMDID_GET_MAC_STATISTICS			DPNI_CMD(0x283)
 
 /* Macros for accessing command fields smaller than 1byte */
 #define DPNI_MASK(field)	\
@@ -1024,5 +1025,11 @@ struct dpni_cmd_sp_enable {
 	uint8_t en;
 };
 
+struct dpni_cmd_get_mac_statistics {
+	uint64_t iova_cnt;
+	uint64_t iova_values;
+	uint32_t num_cnt;
+};
+
 #pragma pack(pop)
 #endif /* _FSL_DPNI_CMD_H */
-- 
2.43.0

[PATCH 09/15] net/dpaa2: setup the speed cap based on the actual MAC

[Prashant Gupta]

From: Ioana Ciornei <ioana.ciornei@nxp.com>

Previously, the speed_capa field from struct rte_eth_dev_info was
populated with all possible speeds that the MACs on the system could
sustain. What this meant is that the bitmap of speed capability did not
reflect what the MAC could do in the current circumstance.

Fix this by using the newly added MC command
dpni_get_mac_speed_capability() which returns a bitmap of
enum dpmac_link_speed. Since the MC API is a newly added one, we check
for the DPNI version to determine is we can use the API, if not the code
will fallback to the procedure used up until now.

Also, we interogate the MC firmware only at probe time to get the needed
into and then we store the information in the private structure to
use it any time .dev_infos_get() is called.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
 drivers/net/dpaa2/dpaa2_ethdev.c    | 87 ++++++++++++++++++++++++++---
 drivers/net/dpaa2/dpaa2_ethdev.h    | 12 ++++
 drivers/net/dpaa2/mc/dpni.c         | 21 +++++++
 drivers/net/dpaa2/mc/fsl_dpmac.h    | 15 +++++
 drivers/net/dpaa2/mc/fsl_dpni.h     |  5 +-
 drivers/net/dpaa2/mc/fsl_dpni_cmd.h |  4 ++
 6 files changed, 134 insertions(+), 10 deletions(-)

diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c
index 5c4c0ae462..529856f704 100644
--- a/drivers/net/dpaa2/dpaa2_ethdev.c
+++ b/drivers/net/dpaa2/dpaa2_ethdev.c
@@ -290,6 +290,79 @@ dpaa2_fw_version_get(struct rte_eth_dev *dev,
 		return 0;
 }
 
+static uint32_t dpaa2_speed_to_rte_link_speed(enum dpmac_link_speed dpmac_speed)
+{
+	switch (dpmac_speed) {
+	case DPMAC_LINK_SPEED_10M:
+		return RTE_ETH_LINK_SPEED_10M;
+	case DPMAC_LINK_SPEED_100M:
+		return RTE_ETH_LINK_SPEED_100M;
+	case DPMAC_LINK_SPEED_1G:
+		return RTE_ETH_LINK_SPEED_1G;
+	case DPMAC_LINK_SPEED_2_5G:
+		return RTE_ETH_LINK_SPEED_2_5G;
+	case DPMAC_LINK_SPEED_5G:
+		return RTE_ETH_LINK_SPEED_5G;
+	case DPMAC_LINK_SPEED_10G:
+		return RTE_ETH_LINK_SPEED_10G;
+	case DPMAC_LINK_SPEED_25G:
+		return RTE_ETH_LINK_SPEED_25G;
+	case DPMAC_LINK_SPEED_40G:
+		return RTE_ETH_LINK_SPEED_40G;
+	case DPMAC_LINK_SPEED_50G:
+		return RTE_ETH_LINK_SPEED_50G;
+	case DPMAC_LINK_SPEED_100G:
+		return RTE_ETH_LINK_SPEED_100G;
+	default:
+		return 0;
+	}
+}
+
+static uint32_t dpaa2_dev_get_speed_capability(struct rte_eth_dev *dev)
+{
+	struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
+	struct dpaa2_dev_priv *priv = dev->data->dev_private;
+	enum dpmac_link_speed speed;
+	uint32_t dpmac_speed_cap;
+	uint32_t speed_capa = 0;
+	int ret;
+
+	/* The dpni_get_mac_supported_eth_if() API is only available starting
+	 * with DPNI ver 8.6.
+	 */
+	if (dpaa2_dev_cmp_dpni_ver(priv, DPNI_GET_MAC_SUPPORTED_IFS_VER_MAJOR,
+				   DPNI_GET_MAC_SUPPORTED_IFS_VER_MINOR) < 0)
+		goto fallback;
+
+	if (priv->ep_dev_type != DPAA2_MAC)
+		goto fallback;
+
+	ret = dpni_get_mac_speed_capability(dpni, CMD_PRI_LOW, priv->token,
+					    &dpmac_speed_cap);
+	if (ret < 0) {
+		DPAA2_PMD_WARN("dpni_get_mac_speed_capability() failed with %d", ret);
+		goto fallback;
+	}
+	for (speed = DPMAC_LINK_SPEED_10M; speed < DPMAC_LINK_SPEED_MAX; speed++) {
+		if ((dpmac_speed_cap & (1 << speed)) == 0)
+			continue;
+
+		speed_capa |= dpaa2_speed_to_rte_link_speed(speed);
+	}
+
+	return speed_capa;
+
+fallback:
+	speed_capa = RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_2_5G |
+		RTE_ETH_LINK_SPEED_10G;
+
+	if (dpaa2_svr_family == SVR_LX2160A)
+		speed_capa |= RTE_ETH_LINK_SPEED_25G | RTE_ETH_LINK_SPEED_40G |
+			RTE_ETH_LINK_SPEED_50G | RTE_ETH_LINK_SPEED_100G;
+
+	return speed_capa;
+}
+
 static int
 dpaa2_dev_info_get(struct rte_eth_dev *dev,
 	struct rte_eth_dev_info *dev_info)
@@ -307,9 +380,6 @@ dpaa2_dev_info_get(struct rte_eth_dev *dev,
 					dev_rx_offloads_nodis;
 	dev_info->tx_offload_capa = dev_tx_offloads_sup |
 					dev_tx_offloads_nodis;
-	dev_info->speed_capa = RTE_ETH_LINK_SPEED_1G |
-			RTE_ETH_LINK_SPEED_2_5G |
-			RTE_ETH_LINK_SPEED_10G;
 	dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
 
 	dev_info->max_hash_mac_addrs = 0;
@@ -326,12 +396,7 @@ dpaa2_dev_info_get(struct rte_eth_dev *dev,
 	dev_info->default_txportconf.ring_size = CONG_ENTER_TX_THRESHOLD;
 	dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC;
 
-	if (dpaa2_svr_family == SVR_LX2160A) {
-		dev_info->speed_capa |= RTE_ETH_LINK_SPEED_25G |
-				RTE_ETH_LINK_SPEED_40G |
-				RTE_ETH_LINK_SPEED_50G |
-				RTE_ETH_LINK_SPEED_100G;
-	}
+	dev_info->speed_capa = priv->speed_capa;
 
 	return 0;
 }
@@ -1130,6 +1195,7 @@ dpaa2_supported_ptypes_get(struct rte_eth_dev *dev, size_t *no_of_elements)
 		/*todo -= add more types */
 		RTE_PTYPE_L2_ETHER,
 		RTE_PTYPE_L3_IPV4,
+
 		RTE_PTYPE_L3_IPV4_EXT,
 		RTE_PTYPE_L3_IPV6,
 		RTE_PTYPE_L3_IPV6_EXT,
@@ -2976,6 +3042,9 @@ dpaa2_dev_init(struct rte_eth_dev *eth_dev)
 	DPAA2_PMD_INFO("%s: netdev created, connected to %s",
 		eth_dev->data->name, dpaa2_dev->ep_name);
 
+
+	priv->speed_capa = dpaa2_dev_get_speed_capability(eth_dev);
+
 	return 0;
 init_err:
 	dpaa2_dev_close(eth_dev);
diff --git a/drivers/net/dpaa2/dpaa2_ethdev.h b/drivers/net/dpaa2/dpaa2_ethdev.h
index 6026b378a7..c4133f604f 100644
--- a/drivers/net/dpaa2/dpaa2_ethdev.h
+++ b/drivers/net/dpaa2/dpaa2_ethdev.h
@@ -400,6 +400,7 @@ struct dpaa2_dev_priv {
 
 	uint16_t dpni_ver_major;
 	uint16_t dpni_ver_minor;
+	uint32_t speed_capa;
 
 	enum rte_dpaa2_dev_type ep_dev_type;   /**< Endpoint Device Type */
 	uint16_t ep_object_id;                 /**< Endpoint DPAA2 Object ID */
@@ -436,6 +437,17 @@ struct dpaa2_dev_priv {
 	LIST_HEAD(shaper_profiles, dpaa2_tm_shaper_profile) shaper_profiles;
 };
 
+#define DPNI_GET_MAC_SUPPORTED_IFS_VER_MAJOR	8
+#define DPNI_GET_MAC_SUPPORTED_IFS_VER_MINOR	6
+
+static inline int dpaa2_dev_cmp_dpni_ver(struct dpaa2_dev_priv *priv,
+					 uint16_t ver_major, uint16_t ver_minor)
+{
+	if (priv->dpni_ver_major == ver_major)
+		return priv->dpni_ver_minor - ver_minor;
+	return priv->dpni_ver_major - ver_major;
+}
+
 int dpaa2_distset_to_dpkg_profile_cfg(uint64_t req_dist_set,
 				      struct dpkg_profile_cfg *kg_cfg);
 
diff --git a/drivers/net/dpaa2/mc/dpni.c b/drivers/net/dpaa2/mc/dpni.c
index f651f29b02..a1f168dd04 100644
--- a/drivers/net/dpaa2/mc/dpni.c
+++ b/drivers/net/dpaa2/mc/dpni.c
@@ -3493,6 +3493,7 @@ int dpni_sp_enable(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token,
 	/* send command to MC */
 	return mc_send_command(mc_io, &cmd);
 }
+
 /**
  * dpni_get_mac_statistics() - Get statistics on the connected DPMAC objects
  * @mc_io:       Pointer to opaque I/O object
@@ -3520,3 +3521,23 @@ int dpni_get_mac_statistics(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_
 
 	return mc_send_command(mc_io, &cmd);
 }
+
+int dpni_get_mac_speed_capability(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token,
+				  uint32_t *speed_cap)
+{
+	struct dpni_rsp_mac_speed_cap *rsp_params;
+	struct mc_command cmd = { 0 };
+	int err;
+
+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_MAC_SPEED_CAPABILITY,
+					  cmd_flags, token);
+
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	rsp_params = (struct dpni_rsp_mac_speed_cap *)cmd.params;
+	*speed_cap = le32_to_cpu(rsp_params->speed_cap);
+
+	return 0;
+}
diff --git a/drivers/net/dpaa2/mc/fsl_dpmac.h b/drivers/net/dpaa2/mc/fsl_dpmac.h
index 375d646cfc..61d7573a4b 100644
--- a/drivers/net/dpaa2/mc/fsl_dpmac.h
+++ b/drivers/net/dpaa2/mc/fsl_dpmac.h
@@ -67,6 +67,21 @@ enum dpmac_eth_if {
 	DPMAC_ETH_IF_1000BASEX,
 	DPMAC_ETH_IF_USXGMII,
 };
+
+enum dpmac_link_speed {
+	DPMAC_LINK_SPEED_10M = 0,
+	DPMAC_LINK_SPEED_100M,
+	DPMAC_LINK_SPEED_1G,
+	DPMAC_LINK_SPEED_2_5G,
+	DPMAC_LINK_SPEED_5G,
+	DPMAC_LINK_SPEED_10G,
+	DPMAC_LINK_SPEED_25G,
+	DPMAC_LINK_SPEED_40G,
+	DPMAC_LINK_SPEED_50G,
+	DPMAC_LINK_SPEED_100G,
+	DPMAC_LINK_SPEED_MAX,
+};
+
 /*
  * @DPMAC_FEC_NONE: RS-FEC (enabled by default) is disabled
  * @DPMAC_FEC_RS: RS-FEC (Clause 91) mode configured
diff --git a/drivers/net/dpaa2/mc/fsl_dpni.h b/drivers/net/dpaa2/mc/fsl_dpni.h
index 2f8125314c..8d28b8ce76 100644
--- a/drivers/net/dpaa2/mc/fsl_dpni.h
+++ b/drivers/net/dpaa2/mc/fsl_dpni.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
  *
  * Copyright 2013-2016 Freescale Semiconductor Inc.
- * Copyright 2016-2023 NXP
+ * Copyright 2016-2025 NXP
  *
  */
 #ifndef __FSL_DPNI_H
@@ -2017,4 +2017,7 @@ int dpni_sp_enable(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token,
 int dpni_get_mac_statistics(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token,
 			    uint64_t iova_cnt, uint64_t iova_values, uint32_t num_cnt);
 
+int dpni_get_mac_speed_capability(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token,
+				  uint32_t *speed_cap);
+
 #endif /* __FSL_DPNI_H */
diff --git a/drivers/net/dpaa2/mc/fsl_dpni_cmd.h b/drivers/net/dpaa2/mc/fsl_dpni_cmd.h
index f653f2c0e4..cf4558d540 100644
--- a/drivers/net/dpaa2/mc/fsl_dpni_cmd.h
+++ b/drivers/net/dpaa2/mc/fsl_dpni_cmd.h
@@ -132,6 +132,7 @@
 #define DPNI_CMDID_SET_QUEUE_TX_CONFIRMATION_MODE	DPNI_CMD(0x281)
 #define DPNI_CMDID_GET_QUEUE_TX_CONFIRMATION_MODE	DPNI_CMD(0x282)
 #define DPNI_CMDID_GET_MAC_STATISTICS			DPNI_CMD(0x283)
+#define DPNI_CMDID_GET_MAC_SPEED_CAPABILITY		DPNI_CMD(0x284)
 
 /* Macros for accessing command fields smaller than 1byte */
 #define DPNI_MASK(field)	\
@@ -1031,5 +1032,8 @@ struct dpni_cmd_get_mac_statistics {
 	uint32_t num_cnt;
 };
 
+struct dpni_rsp_mac_speed_cap {
+	uint32_t speed_cap;
+};
 #pragma pack(pop)
 #endif /* _FSL_DPNI_CMD_H */
-- 
2.43.0

[PATCH 10/15] drivers: dpaa2 upgrade fslmc base FW to 10.39.0

[Prashant Gupta]

From: Hemant Agrawal <hemant.agrawal@nxp.com>

This patch upgrades the MC firmware release API compatibility
to 10.39.0.
the main changes are:
dpni - dpmac stats APIs
RTC - default 1588 clock config support

Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
 drivers/bus/fslmc/bus_fslmc_driver.h |  1 +
 drivers/bus/fslmc/mc/dpbp.c          | 78 +++++++++++++++++++++++++++-
 drivers/bus/fslmc/mc/dprc.c          |  2 +
 drivers/bus/fslmc/mc/fsl_dpbp.h      | 41 ++++++++++++++-
 drivers/bus/fslmc/mc/fsl_dpmng.h     |  4 +-
 drivers/bus/fslmc/mc/fsl_dprc.h      |  1 +
 drivers/net/dpaa2/dpaa2_mux.c        |  8 +--
 drivers/net/dpaa2/mc/dpkg.c          |  7 ++-
 drivers/net/dpaa2/mc/dprtc.c         | 38 +++++++++++++-
 drivers/net/dpaa2/mc/fsl_dpdmux.h    | 13 +++--
 drivers/net/dpaa2/mc/fsl_dpkg.h      |  7 ++-
 drivers/net/dpaa2/mc/fsl_dpni.h      | 29 +++++++++--
 drivers/net/dpaa2/mc/fsl_dprtc.h     | 39 +++++++++++++-
 drivers/net/dpaa2/mc/fsl_dprtc_cmd.h |  7 ++-
 14 files changed, 249 insertions(+), 26 deletions(-)

diff --git a/drivers/bus/fslmc/bus_fslmc_driver.h b/drivers/bus/fslmc/bus_fslmc_driver.h
index 442de1a3fb..928193f0c0 100644
--- a/drivers/bus/fslmc/bus_fslmc_driver.h
+++ b/drivers/bus/fslmc/bus_fslmc_driver.h
@@ -81,6 +81,7 @@ enum rte_dpaa2_dev_type {
 	DPAA2_MPORTAL,  /**< DPMCP type device */
 	DPAA2_QDMA,     /**< DPDMAI type device */
 	DPAA2_MUX,	/**< DPDMUX type device */
+	DPAA2_SW,       /**< DPSW type device */
 	DPAA2_DPRTC,	/**< DPRTC type device */
 	DPAA2_DPRC,	/**< DPRC type device */
 	DPAA2_MAC,	/**< DPMAC type device */
diff --git a/drivers/bus/fslmc/mc/dpbp.c b/drivers/bus/fslmc/mc/dpbp.c
index 08f24d33e8..5529a1fe9c 100644
--- a/drivers/bus/fslmc/mc/dpbp.c
+++ b/drivers/bus/fslmc/mc/dpbp.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
  *
  * Copyright 2013-2016 Freescale Semiconductor Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2017, 2025 NXP
  *
  */
 #include <fsl_mc_sys.h>
@@ -362,3 +362,79 @@ int dpbp_get_num_free_bufs(struct fsl_mc_io *mc_io,
 
 	return 0;
 }
+
+/**
+ * dpbp_set_notifications() - Set notifications towards software
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPBP object
+ * @cfg:	notifications configuration
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+RTE_EXPORT_INTERNAL_SYMBOL(dpbp_set_notifications)
+int dpbp_set_notifications(struct fsl_mc_io *mc_io,
+	uint32_t cmd_flags,
+	uint16_t token,
+	struct dpbp_notification_cfg *cfg)
+{
+	struct dpbp_cmd_set_notifications *cmd_params;
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPBP_CMDID_SET_NOTIFICATIONS,
+			cmd_flags, token);
+	cmd_params = (struct dpbp_cmd_set_notifications *)cmd.params;
+	cmd_params->depletion_entry = cpu_to_le32(cfg->depletion_entry);
+	cmd_params->depletion_exit = cpu_to_le32(cfg->depletion_exit);
+	cmd_params->surplus_entry = cpu_to_le32(cfg->surplus_entry);
+	cmd_params->surplus_exit = cpu_to_le32(cfg->surplus_exit);
+	cmd_params->options = cpu_to_le32(cfg->options);
+	cmd_params->message_ctx = cpu_to_le64(cfg->message_ctx);
+	cmd_params->message_iova = cpu_to_le64(cfg->message_iova);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+/**
+ * dpbp_get_notifications() - Get the notifications configuration
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPBP object
+ * @cfg:	notifications configuration
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+RTE_EXPORT_INTERNAL_SYMBOL(dpbp_get_notifications)
+int dpbp_get_notifications(struct fsl_mc_io *mc_io,
+	uint32_t cmd_flags,
+	uint16_t token,
+	struct dpbp_notification_cfg *cfg)
+{
+	struct dpbp_rsp_get_notifications *rsp_params;
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_NOTIFICATIONS,
+			  cmd_flags,
+			  token);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	rsp_params = (struct dpbp_rsp_get_notifications *)cmd.params;
+	cfg->depletion_entry = le32_to_cpu(rsp_params->depletion_entry);
+	cfg->depletion_exit = le32_to_cpu(rsp_params->depletion_exit);
+	cfg->surplus_entry = le32_to_cpu(rsp_params->surplus_entry);
+	cfg->surplus_exit = le32_to_cpu(rsp_params->surplus_exit);
+	cfg->options = le32_to_cpu(rsp_params->options);
+	cfg->message_ctx = le64_to_cpu(rsp_params->message_ctx);
+	cfg->message_iova = le64_to_cpu(rsp_params->message_iova);
+
+	return 0;
+}
diff --git a/drivers/bus/fslmc/mc/dprc.c b/drivers/bus/fslmc/mc/dprc.c
index 491081c7c8..5f04ead20c 100644
--- a/drivers/bus/fslmc/mc/dprc.c
+++ b/drivers/bus/fslmc/mc/dprc.c
@@ -8,6 +8,7 @@
 #include <fsl_mc_cmd.h>
 #include <fsl_dprc.h>
 #include <fsl_dprc_cmd.h>
+#include <eal_export.h>
 
 /** @addtogroup dprc
  * @{
@@ -90,6 +91,7 @@ int dprc_close(struct fsl_mc_io *mc_io,
  *
  * Return:     '0' on Success; -ENAVAIL if connection does not exist.
  */
+RTE_EXPORT_INTERNAL_SYMBOL(dprc_get_connection)
 int dprc_get_connection(struct fsl_mc_io *mc_io,
 			uint32_t cmd_flags,
 			uint16_t token,
diff --git a/drivers/bus/fslmc/mc/fsl_dpbp.h b/drivers/bus/fslmc/mc/fsl_dpbp.h
index 8a021f55f1..c79b511715 100644
--- a/drivers/bus/fslmc/mc/fsl_dpbp.h
+++ b/drivers/bus/fslmc/mc/fsl_dpbp.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
  *
  * Copyright 2013-2016 Freescale Semiconductor Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2017, 2025 NXP
  *
  */
 #ifndef __FSL_DPBP_H
@@ -16,6 +16,34 @@
 
 struct fsl_mc_io;
 
+/**
+ * struct dpbp_notification_cfg - Structure representing DPBP notifications
+ *	towards software
+ * @depletion_entry: below this threshold the pool is "depleted";
+ *	set it to '0' to disable it
+ * @depletion_exit: greater than or equal to this threshold the pool exit its
+ *	"depleted" state
+ * @surplus_entry: above this threshold the pool is in "surplus" state;
+ *	set it to '0' to disable it
+ * @surplus_exit: less than or equal to this threshold the pool exit its
+ *	"surplus" state
+ * @message_iova: MUST be given if either 'depletion_entry' or 'surplus_entry'
+ *	is not '0' (enable); I/O virtual address (must be in DMA-able memory),
+ *	must be 16B aligned.
+ * @message_ctx: The context that will be part of the BPSCN message and will
+ *	be written to 'message_iova'
+ * @options: Mask of available options; use 'DPBP_NOTIF_OPT_<X>' values
+ */
+struct dpbp_notification_cfg {
+	uint32_t depletion_entry;
+	uint32_t depletion_exit;
+	uint32_t surplus_entry;
+	uint32_t surplus_exit;
+	uint64_t message_iova;
+	uint64_t message_ctx;
+	uint32_t options;
+};
+
 __rte_internal
 int dpbp_open(struct fsl_mc_io *mc_io,
 	      uint32_t cmd_flags,
@@ -25,7 +53,18 @@ int dpbp_open(struct fsl_mc_io *mc_io,
 int dpbp_close(struct fsl_mc_io *mc_io,
 	       uint32_t cmd_flags,
 	       uint16_t token);
+__rte_internal
+int dpbp_set_notifications(struct fsl_mc_io *mc_io,
+		uint32_t cmd_flags,
+		uint16_t token,
+		struct dpbp_notification_cfg *cfg);
+__rte_internal
+int dpbp_get_notifications(struct fsl_mc_io *mc_io,
+		uint32_t cmd_flags,
+		uint16_t token,
+		struct dpbp_notification_cfg *cfg);
 
+#define DPBP_NOTIF_OPT_WRIOP               0x00010000
 /**
  * struct dpbp_cfg - Structure representing DPBP configuration
  * @options:	place holder
diff --git a/drivers/bus/fslmc/mc/fsl_dpmng.h b/drivers/bus/fslmc/mc/fsl_dpmng.h
index dfa51b3a86..a7578766e0 100644
--- a/drivers/bus/fslmc/mc/fsl_dpmng.h
+++ b/drivers/bus/fslmc/mc/fsl_dpmng.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
  *
  * Copyright 2013-2015 Freescale Semiconductor Inc.
- * Copyright 2017-2023 NXP
+ * Copyright 2017-2024 NXP
  *
  */
 #ifndef __FSL_DPMNG_H
@@ -20,7 +20,7 @@ struct fsl_mc_io;
  * Management Complex firmware version information
  */
 #define MC_VER_MAJOR 10
-#define MC_VER_MINOR 37
+#define MC_VER_MINOR 39
 
 /**
  * struct mc_version
diff --git a/drivers/bus/fslmc/mc/fsl_dprc.h b/drivers/bus/fslmc/mc/fsl_dprc.h
index 177210c2d4..8c9e482d26 100644
--- a/drivers/bus/fslmc/mc/fsl_dprc.h
+++ b/drivers/bus/fslmc/mc/fsl_dprc.h
@@ -37,6 +37,7 @@ struct dprc_endpoint {
 	uint16_t if_id;
 };
 
+__rte_internal
 int dprc_get_connection(struct fsl_mc_io *mc_io,
 			uint32_t cmd_flags,
 			uint16_t token,
diff --git a/drivers/net/dpaa2/dpaa2_mux.c b/drivers/net/dpaa2/dpaa2_mux.c
index 1908d1e865..9bb1bbca38 100644
--- a/drivers/net/dpaa2/dpaa2_mux.c
+++ b/drivers/net/dpaa2/dpaa2_mux.c
@@ -524,10 +524,12 @@ dpaa2_create_dpdmux_device(int vdev_fd __rte_unused,
 				      __func__);
 			goto init_err;
 		}
-		skip_reset_flags = DPDMUX_SKIP_DEFAULT_INTERFACE
-			| DPDMUX_SKIP_UNICAST_RULES | DPDMUX_SKIP_MULTICAST_RULES;
+		skip_reset_flags = DPDMUX_SKIP_MODIFY_DEFAULT_INTERFACE
+			| DPDMUX_SKIP_UNICAST_RULES | DPDMUX_SKIP_MULTICAST_RULES |
+			DPDMUX_SKIP_RESET_DEFAULT_INTERFACE;
 	} else {
-		skip_reset_flags = DPDMUX_SKIP_DEFAULT_INTERFACE;
+		skip_reset_flags = DPDMUX_SKIP_MODIFY_DEFAULT_INTERFACE |
+			DPDMUX_SKIP_RESET_DEFAULT_INTERFACE;
 	}
 
 	ret = dpdmux_get_api_version(&dpdmux_dev->dpdmux, CMD_PRI_LOW,
diff --git a/drivers/net/dpaa2/mc/dpkg.c b/drivers/net/dpaa2/mc/dpkg.c
index 5db3d092c1..280c1b0764 100644
--- a/drivers/net/dpaa2/mc/dpkg.c
+++ b/drivers/net/dpaa2/mc/dpkg.c
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
  *
- * Copyright 2017-2021, 2023 NXP
+ * Copyright 2017-2021, 2023-2024 NXP
  *
  */
 #include <fsl_mc_sys.h>
@@ -20,8 +20,7 @@
  *	- dpkg_prepare_key_cfg()
  */
 int
-dpkg_prepare_key_cfg(const struct dpkg_profile_cfg *cfg,
-	void *key_cfg_buf)
+dpkg_prepare_key_cfg(const struct dpkg_profile_cfg *cfg, uint8_t *key_cfg_buf)
 {
 	int i, j;
 	struct dpni_ext_set_rx_tc_dist *dpni_ext;
@@ -30,7 +29,7 @@ dpkg_prepare_key_cfg(const struct dpkg_profile_cfg *cfg,
 	if (cfg->num_extracts > DPKG_MAX_NUM_OF_EXTRACTS)
 		return -EINVAL;
 
-	dpni_ext = key_cfg_buf;
+	dpni_ext = (struct dpni_ext_set_rx_tc_dist *)key_cfg_buf;
 	dpni_ext->num_extracts = cfg->num_extracts;
 
 	for (i = 0; i < cfg->num_extracts; i++) {
diff --git a/drivers/net/dpaa2/mc/dprtc.c b/drivers/net/dpaa2/mc/dprtc.c
index 36e62eb0c3..18f23e2fe3 100644
--- a/drivers/net/dpaa2/mc/dprtc.c
+++ b/drivers/net/dpaa2/mc/dprtc.c
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
- * Copyright 2019-2021 NXP
+ * Copyright 2019-2024 NXP
  */
 #include <fsl_mc_sys.h>
 #include <fsl_mc_cmd.h>
@@ -329,6 +329,42 @@ int dprtc_set_clock_offset(struct fsl_mc_io *mc_io,
 	return mc_send_command(mc_io, &cmd);
 }
 
+/**
+ * dprtc_get_clock_offset() - Gets the clock's offset
+ * (usually relative to another clock).
+ *
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPRTC object
+ * @offset:	Returned clock offset (in nanoseconds).
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dprtc_get_clock_offset(struct fsl_mc_io *mc_io,
+			   uint32_t cmd_flags,
+			   uint16_t token,
+			   int64_t *offset)
+{
+	struct dprtc_rsp_get_clock_offset *rsp_params;
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_GET_CLOCK_OFFSET,
+					  cmd_flags,
+					  token);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	rsp_params = (struct dprtc_rsp_get_clock_offset *)cmd.params;
+	*offset = le64_to_cpu(rsp_params->offset);
+
+	return 0;
+}
+
 /**
  * dprtc_set_freq_compensation() - Sets a new frequency compensation value.
  *
diff --git a/drivers/net/dpaa2/mc/fsl_dpdmux.h b/drivers/net/dpaa2/mc/fsl_dpdmux.h
index 97b09e59f9..2db4abf234 100644
--- a/drivers/net/dpaa2/mc/fsl_dpdmux.h
+++ b/drivers/net/dpaa2/mc/fsl_dpdmux.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
  *
  * Copyright 2013-2016 Freescale Semiconductor Inc.
- * Copyright 2018-2023 NXP
+ * Copyright 2018-2024 NXP
  *
  */
 #ifndef __FSL_DPDMUX_H
@@ -53,6 +53,9 @@ int dpdmux_close(struct fsl_mc_io *mc_io,
  */
 #define DPDMUX_IRQ_EVENT_LINK_CHANGED	0x0001
 
+/* DPDMUX_IRQ_EVENT_ENDPOINT_CHANGED - indicates a change in endpoint */
+#define DPDMUX_IRQ_EVENT_ENDPOINT_CHANGED	0x0002
+
 /**
  * enum dpdmux_manip - DPDMUX manipulation operations
  * @DPDMUX_MANIP_NONE:	No manipulation on frames
@@ -143,15 +146,15 @@ int dpdmux_reset(struct fsl_mc_io *mc_io,
 		 uint16_t token);
 
 /**
- *Setting 1 DPDMUX_RESET will not reset default interface
+ *Setting 1 DPDMUX_RESET will not modify default interface after reset
  */
-#define DPDMUX_SKIP_DEFAULT_INTERFACE	0x01
+#define DPDMUX_SKIP_MODIFY_DEFAULT_INTERFACE	0x01
 /**
- *Setting 1 DPDMUX_RESET will not reset unicast rules
+ *Setting 2 DPDMUX_RESET will not reset unicast rules
  */
 #define DPDMUX_SKIP_UNICAST_RULES	0x02
 /**
- *Setting 1 DPDMUX_RESET will not reset multicast rules
+ *Setting 3 DPDMUX_RESET will not reset multicast rules
  */
 #define DPDMUX_SKIP_MULTICAST_RULES	0x04
 /**
diff --git a/drivers/net/dpaa2/mc/fsl_dpkg.h b/drivers/net/dpaa2/mc/fsl_dpkg.h
index 834c765513..19fbae224b 100644
--- a/drivers/net/dpaa2/mc/fsl_dpkg.h
+++ b/drivers/net/dpaa2/mc/fsl_dpkg.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
  * Copyright 2013-2015 Freescale Semiconductor Inc.
- * Copyright 2016-2023 NXP
+ * Copyright 2016-2024 NXP
  *
  */
 #ifndef __FSL_DPKG_H_
@@ -180,8 +180,7 @@ struct dpni_ext_set_rx_tc_dist {
 	struct dpni_dist_extract extracts[DPKG_MAX_NUM_OF_EXTRACTS];
 };
 
-int
-dpkg_prepare_key_cfg(const struct dpkg_profile_cfg *cfg,
-	void *key_cfg_buf);
+int dpkg_prepare_key_cfg(const struct dpkg_profile_cfg *cfg,
+			 uint8_t *key_cfg_buf);
 
 #endif /* __FSL_DPKG_H_ */
diff --git a/drivers/net/dpaa2/mc/fsl_dpni.h b/drivers/net/dpaa2/mc/fsl_dpni.h
index 8d28b8ce76..f7e4c226ed 100644
--- a/drivers/net/dpaa2/mc/fsl_dpni.h
+++ b/drivers/net/dpaa2/mc/fsl_dpni.h
@@ -296,6 +296,9 @@ int dpni_reset(struct fsl_mc_io *mc_io,
  */
 #define DPNI_IRQ_EVENT_LINK_CHANGED		0x00000001
 
+/* DPNI_IRQ_EVENT_ENDPOINT_CHANGED - indicates a change in endpoint */
+#define DPNI_IRQ_EVENT_ENDPOINT_CHANGED       0x00000002
+
 int dpni_set_irq_enable(struct fsl_mc_io *mc_io,
 			uint32_t cmd_flags,
 			uint16_t token,
@@ -574,8 +577,9 @@ int dpni_set_buffer_layout(struct fsl_mc_io *mc_io,
  * @DPNI_OFF_RX_L4_CSUM: Rx L4 checksum validation
  * @DPNI_OFF_TX_L3_CSUM: Tx L3 checksum generation
  * @DPNI_OFF_TX_L4_CSUM: Tx L4 checksum generation
- * @DPNI_OPT_FLCTYPE_HASH: flow context will be generated by WRIOP for AIOP or
- *			   for CPU
+ * @DPNI_OPT_FLCTYPE_HASH: flow context will be generated by WRIOP for AIOP or for CPU
+ * @DPNI_HEADER_STASHING: frame header will be stashed by WRIOP in core cache
+ * @DPNI_PAYLOAD_STASHING: frame payload will be stashed by WRIOP in core cache
  */
 enum dpni_offload {
 	DPNI_OFF_RX_L3_CSUM,
@@ -631,6 +635,7 @@ int dpni_get_tx_data_offset(struct fsl_mc_io *mc_io,
 			    uint16_t *data_offset);
 
 #define DPNI_STATISTICS_CNT		7
+#define DPNI_STATISTICS_32_CNT		14
 
 /**
  * union dpni_statistics - Union describing the DPNI statistics
@@ -986,7 +991,18 @@ struct dpni_tx_schedule_cfg {
  * struct dpni_tx_priorities_cfg - Structure representing transmission
  *					priorities for DPNI TCs
  * @channel_idx: channel to perform the configuration
- * @tc_sched:	An array of traffic-classes
+ * @tc_sched: An array of traffic-classes which should be used in the
+ * following way:
+ *   - If max_tx_tcs <= 8: the tc_sched[n] struct will host the configuration
+ *   requested for TC#n
+ *   - If max_tx_tcs > 8: the tc_sched[n] struct will host the configuration
+ *   requeted for TC#(8 + n). In this case, the first 8 TCs are configured by
+ *   MC in strict priority order and cannot be changed.
+ *   The only accepted configuration in this case is:
+ *    - TCs [8-12) will be part of WEIGHTED_A group
+ *    - TCs [12-16) will be part of WEIGHTED_B group
+ *   Any other configuration will get rejected by the MC firmware. The
+ *   delta_bandwidth for each TC can be used as usual.
  * @prio_group_A: Priority of group A
  * @prio_group_B: Priority of group B
  * @separate_groups: Treat A and B groups as separate
@@ -1949,6 +1965,10 @@ int dpni_get_custom_tpid(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t t
  *	@peer_delay: For peer-to-peer transparent clocks add this value to the
  *		correction field in addition to the transient time update. The
  *		value expresses nanoseconds.
+ *	@ptp_onestep_reg_base: 1588 SINGLE_STEP register base address. This address
+ *			  is used to update directly the register contents.
+ *			  User has to create an address mapping for it.
+ *			  It's used  in dpni_get_single_step_cfg only.
  */
 struct dpni_single_step_cfg {
 	uint8_t en;
@@ -2020,4 +2040,7 @@ int dpni_get_mac_statistics(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_
 int dpni_get_mac_speed_capability(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token,
 				  uint32_t *speed_cap);
 
+int dpni_get_mac_statistics(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token,
+			    uint64_t iova_cnt, uint64_t iova_values, uint32_t num_cnt);
+
 #endif /* __FSL_DPNI_H */
diff --git a/drivers/net/dpaa2/mc/fsl_dprtc.h b/drivers/net/dpaa2/mc/fsl_dprtc.h
index 84ab158444..06ff8ecb19 100644
--- a/drivers/net/dpaa2/mc/fsl_dprtc.h
+++ b/drivers/net/dpaa2/mc/fsl_dprtc.h
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
- * Copyright 2019-2021 NXP
+ * Copyright 2019-2024 NXP
  */
 #ifndef __FSL_DPRTC_H
 #define __FSL_DPRTC_H
@@ -11,6 +11,38 @@
 
 struct fsl_mc_io;
 
+/**
+ * Number of irq's
+ */
+#define DPRTC_MAX_IRQ_NUM			1
+#define DPRTC_IRQ_INDEX				0
+
+/**
+ * Interrupt event masks:
+ */
+
+/**
+ * Interrupt event mask indicating alarm event had occurred
+ */
+#define DPRTC_EVENT_ALARM			0x40000000
+/**
+ * Interrupt event mask indicating periodic pulse 1 event had occurred
+ */
+#define DPRTC_EVENT_PPS				0x08000000
+/**
+ * Interrupt event mask indicating periodic pulse 2 event had occurred
+ */
+#define DPRTC_EVENT_PPS2            0x04000000
+/**
+ * Interrupt event mask indicating External trigger 1 new timestamp sample event had occurred
+ */
+#define DPRTC_EVENT_ETS1			0x00800000
+/**
+ * Interrupt event mask indicating External trigger 2 new timestamp sample event had occurred
+ */
+#define DPRTC_EVENT_ETS2			0x00400000
+
+
 int dprtc_open(struct fsl_mc_io *mc_io,
 	       uint32_t cmd_flags,
 	       int dprtc_id,
@@ -61,6 +93,11 @@ int dprtc_set_clock_offset(struct fsl_mc_io *mc_io,
 			   uint16_t token,
 			   int64_t offset);
 
+int dprtc_get_clock_offset(struct fsl_mc_io *mc_io,
+			   uint32_t cmd_flags,
+			   uint16_t token,
+			   int64_t *offset);
+
 int dprtc_set_freq_compensation(struct fsl_mc_io *mc_io,
 		  uint32_t cmd_flags,
 		  uint16_t token,
diff --git a/drivers/net/dpaa2/mc/fsl_dprtc_cmd.h b/drivers/net/dpaa2/mc/fsl_dprtc_cmd.h
index 61aaa4daab..eaefe18460 100644
--- a/drivers/net/dpaa2/mc/fsl_dprtc_cmd.h
+++ b/drivers/net/dpaa2/mc/fsl_dprtc_cmd.h
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
- * Copyright 2019-2021 NXP
+ * Copyright 2019-2024 NXP
  */
 #include <fsl_mc_sys.h>
 #ifndef _FSL_DPRTC_CMD_H
@@ -42,6 +42,7 @@
 #define DPRTC_CMDID_CLEAR_EXT_TRIGGER		DPRTC_CMD(0x1d9)
 #define DPRTC_CMDID_GET_EXT_TRIGGER_TIMESTAMP	DPRTC_CMD(0x1dA)
 #define DPRTC_CMDID_SET_FIPER_LOOPBACK	DPRTC_CMD(0x1dB)
+#define DPRTC_CMDID_GET_CLOCK_OFFSET		DPRTC_CMD(0x1dC)
 
 /* Macros for accessing command fields smaller than 1byte */
 #define DPRTC_MASK(field)        \
@@ -78,6 +79,10 @@ struct dprtc_cmd_set_clock_offset {
 	uint64_t offset;
 };
 
+struct dprtc_rsp_get_clock_offset {
+	uint64_t offset;
+};
+
 struct dprtc_get_freq_compensation {
 	uint32_t freq_compensation;
 };
-- 
2.43.0

[PATCH 11/15] net/dpaa2: replace global variable to driver flag

[Prashant Gupta]

From: Hemant Agrawal <hemant.agrawal@nxp.com>

This patch replaces the various global variable with
driver specific flag and align.

Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
 drivers/net/dpaa2/dpaa2_ethdev.c | 29 +++++++++++++++----------
 drivers/net/dpaa2/dpaa2_ethdev.h | 36 +++++++++++++++++++-------------
 drivers/net/dpaa2/dpaa2_rxtx.c   |  4 ++--
 3 files changed, 42 insertions(+), 27 deletions(-)

diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c
index 529856f704..56c23e4717 100644
--- a/drivers/net/dpaa2/dpaa2_ethdev.c
+++ b/drivers/net/dpaa2/dpaa2_ethdev.c
@@ -73,9 +73,6 @@ bool dpaa2_enable_ts[RTE_MAX_ETHPORTS];
 uint64_t dpaa2_timestamp_rx_dynflag;
 int dpaa2_timestamp_dynfield_offset = -1;
 
-/* Enable error queue */
-bool dpaa2_enable_err_queue;
-
 bool dpaa2_print_parser_result;
 
 #define MAX_NB_RX_DESC		11264
@@ -507,7 +504,7 @@ dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)
 			goto fail;
 	}
 
-	if (dpaa2_enable_err_queue) {
+	if (priv->flags & DPAAX_RX_ERROR_QUEUE_FLAG) {
 		priv->rx_err_vq = rte_zmalloc("dpni_rx_err",
 			sizeof(struct dpaa2_queue), 0);
 		if (!priv->rx_err_vq) {
@@ -584,7 +581,7 @@ dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)
 		priv->rx_vq[i--] = NULL;
 	}
 
-	if (dpaa2_enable_err_queue) {
+	if (priv->flags & DPAAX_RX_ERROR_QUEUE_FLAG) {
 		dpaa2_q = priv->rx_err_vq;
 		dpaa2_queue_storage_free(dpaa2_q, RTE_MAX_LCORE);
 	}
@@ -1331,7 +1328,7 @@ dpaa2_dev_start(struct rte_eth_dev *dev)
 		dpaa2_q->fqid = qid.fqid;
 	}
 
-	if (dpaa2_enable_err_queue) {
+	if (priv->flags & DPAAX_RX_ERROR_QUEUE_FLAG) {
 		ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
 				     DPNI_QUEUE_RX_ERR, 0, 0, &cfg, &qid);
 		if (ret) {
@@ -2797,6 +2794,17 @@ dpaa2_dev_init(struct rte_eth_dev *eth_dev)
 	dpni_dev->regs = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX);
 	eth_dev->process_private = dpni_dev;
 
+	/* RX no prefetch mode? */
+	if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) {
+		priv->flags |= DPAA2_NO_PREFETCH_RX;
+		DPAA2_PMD_INFO("No RX prefetch mode");
+	}
+
+	if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) {
+		priv->flags |= DPAA2_RX_LOOPBACK_MODE;
+		DPAA2_PMD_INFO("Rx loopback mode");
+	}
+
 	/* For secondary processes, the primary has done all the work */
 	if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 		/* In case of secondary, only burst and ops API need to be
@@ -2804,10 +2812,9 @@ dpaa2_dev_init(struct rte_eth_dev *eth_dev)
 		 */
 		eth_dev->dev_ops = &dpaa2_ethdev_ops;
 		eth_dev->rx_queue_count = dpaa2_dev_rx_queue_count;
-		if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE))
+		if (priv->flags & DPAA2_RX_LOOPBACK_MODE)
 			eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
-		else if (dpaa2_get_devargs(dev->devargs,
-					DRIVER_NO_PREFETCH_MODE))
+		else if (priv->flags & DPAA2_NO_PREFETCH_RX)
 			eth_dev->rx_pkt_burst = dpaa2_dev_rx;
 		else
 			eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
@@ -2898,8 +2905,8 @@ dpaa2_dev_init(struct rte_eth_dev *eth_dev)
 	}
 
 	if (dpaa2_get_devargs(dev->devargs, DRIVER_ERROR_QUEUE)) {
-		dpaa2_enable_err_queue = 1;
-		DPAA2_PMD_INFO("Enable DMA error checks");
+		priv->flags |= DPAAX_RX_ERROR_QUEUE_FLAG;
+		DPAA2_PMD_INFO("Enable error queue");
 	}
 
 	if (getenv("DPAA2_PRINT_RX_PARSER_RESULT"))
diff --git a/drivers/net/dpaa2/dpaa2_ethdev.h b/drivers/net/dpaa2/dpaa2_ethdev.h
index c4133f604f..f4adb76bb6 100644
--- a/drivers/net/dpaa2/dpaa2_ethdev.h
+++ b/drivers/net/dpaa2/dpaa2_ethdev.h
@@ -68,26 +68,36 @@
 /* Enable TX Congestion control support
  * default is disable
  */
-#define DPAA2_TX_CGR_OFF	0x01
+#define DPAA2_TX_CGR_OFF	RTE_BIT32(0)
 
 /* Disable RX tail drop, default is enable */
-#define DPAA2_RX_TAILDROP_OFF	0x04
+#define DPAA2_RX_TAILDROP_OFF	RTE_BIT32(2)
+
+/* Disable prefetch Rx mode to get exact requested packets */
+#define DPAA2_NO_PREFETCH_RX	RTE_BIT32(3)
+
+/* Driver level loop mode to simply transmit the ingress traffic */
+#define DPAA2_RX_LOOPBACK_MODE	RTE_BIT32(4)
+
+/* HW loopback the egress traffic to self ingress*/
+#define DPAA2_TX_MAC_LOOPBACK_MODE	RTE_BIT32(5)
+
+#define DPAA2_TX_SERDES_LOOPBACK_MODE	RTE_BIT32(6)
+
+#define DPAA2_TX_DPNI_LOOPBACK_MODE	RTE_BIT32(7)
+
 /* Tx confirmation enabled */
-#define DPAA2_TX_CONF_ENABLE	0x08
+#define DPAA2_TX_CONF_ENABLE	RTE_BIT32(8)
 
 /* Tx dynamic confirmation enabled,
  * only valid with Tx confirmation enabled.
  */
-#define DPAA2_TX_DYNAMIC_CONF_ENABLE	0x10
-/* DPDMUX index for DPMAC */
-#define DPAA2_DPDMUX_DPMAC_IDX 0
-
-/* HW loopback the egress traffic to self ingress*/
-#define DPAA2_TX_MAC_LOOPBACK_MODE 0x20
+#define DPAA2_TX_DYNAMIC_CONF_ENABLE	RTE_BIT32(9)
 
-#define DPAA2_TX_SERDES_LOOPBACK_MODE 0x40
+#define DPAAX_RX_ERROR_QUEUE_FLAG	RTE_BIT32(11)
 
-#define DPAA2_TX_DPNI_LOOPBACK_MODE 0x80
+/* DPDMUX index for DPMAC */
+#define DPAA2_DPDMUX_DPMAC_IDX 0
 
 #define DPAA2_TX_LOOPBACK_MODE \
 	(DPAA2_TX_MAC_LOOPBACK_MODE | \
@@ -167,8 +177,6 @@ extern const struct rte_flow_ops dpaa2_flow_ops;
 
 extern const struct rte_tm_ops dpaa2_tm_ops;
 
-extern bool dpaa2_enable_err_queue;
-
 extern bool dpaa2_print_parser_result;
 
 #define DPAA2_FAPR_SIZE \
@@ -384,7 +392,7 @@ struct dpaa2_dev_priv {
 	struct dpaa2_bp_list *bp_list; /**<Attached buffer pool list */
 	void *tx_conf_vq[MAX_TX_QUEUES * DPAA2_MAX_CHANNELS];
 	void *rx_err_vq;
-	uint8_t flags; /*dpaa2 config flags */
+	uint32_t flags; /*dpaa2 config flags */
 	uint8_t max_mac_filters;
 	uint8_t max_vlan_filters;
 	uint8_t num_rx_tc;
diff --git a/drivers/net/dpaa2/dpaa2_rxtx.c b/drivers/net/dpaa2/dpaa2_rxtx.c
index 7caccfa469..8f932be635 100644
--- a/drivers/net/dpaa2/dpaa2_rxtx.c
+++ b/drivers/net/dpaa2/dpaa2_rxtx.c
@@ -753,7 +753,7 @@ dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
 
 	q_storage = dpaa2_q->q_storage[rte_lcore_id()];
 
-	if (unlikely(dpaa2_enable_err_queue))
+	if (unlikely(priv->flags & DPAAX_RX_ERROR_QUEUE_FLAG))
 		dump_err_pkts(priv->rx_err_vq);
 
 	if (unlikely(!DPAA2_PER_LCORE_ETHRX_DPIO)) {
@@ -994,7 +994,7 @@ dpaa2_dev_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
 	struct rte_eth_dev_data *eth_data = dpaa2_q->eth_data;
 	struct dpaa2_dev_priv *priv = eth_data->dev_private;
 
-	if (unlikely(dpaa2_enable_err_queue))
+	if (unlikely(priv->flags & DPAAX_RX_ERROR_QUEUE_FLAG))
 		dump_err_pkts(priv->rx_err_vq);
 
 	if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
-- 
2.43.0

[PATCH 12/15] net/dpaa2: add devargs to drop parse packets in HW

[Prashant Gupta]

From: Hemant Agrawal <hemant.agrawal@nxp.com>

This patch add support to allow to drop HW parser error
pkts in DPAA2 hardware

Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
 doc/guides/nics/dpaa2.rst        |  4 ++++
 drivers/net/dpaa2/dpaa2_ethdev.c | 11 ++++++++++-
 drivers/net/dpaa2/dpaa2_ethdev.h |  3 +++
 3 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/doc/guides/nics/dpaa2.rst b/doc/guides/nics/dpaa2.rst
index 94bf1907df..782220b4cd 100644
--- a/doc/guides/nics/dpaa2.rst
+++ b/doc/guides/nics/dpaa2.rst
@@ -482,6 +482,10 @@ for details.
   In this mode tx conf queues need to be polled to free the buffers.
   e.g. ``fslmc:dpni.1,drv_tx_conf=1``
 
+* Use dev arg option  ``drv_rx_parse_drop=1`` to configure the system to start
+  dropping the error packets in hardware (parse errors).
+  e.g. ``fslmc:dpni.1,drv_rx_parse_drop=1``
+
 * Use dev arg option  ``drv_error_queue=1`` to enable Packets in Error queue.
   DPAA2 hardware drops the error packet in hardware. This option enables the
   hardware to not drop the error packet and let the driver dump the error
diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c
index 56c23e4717..5b72243346 100644
--- a/drivers/net/dpaa2/dpaa2_ethdev.c
+++ b/drivers/net/dpaa2/dpaa2_ethdev.c
@@ -34,6 +34,7 @@
 #define DRIVER_LOOPBACK_MODE "drv_loopback"
 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch"
 #define DRIVER_TX_CONF "drv_tx_conf"
+#define DRIVER_RX_PARSE_ERR_DROP "drv_rx_parse_drop"
 #define DRIVER_ERROR_QUEUE  "drv_err_queue"
 #define CHECK_INTERVAL         100  /* 100ms */
 #define MAX_REPEAT_TIME        90   /* 9s (90 * 100ms) in total */
@@ -1349,7 +1350,8 @@ dpaa2_dev_start(struct rte_eth_dev *dev)
 		err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE;
 
 		/* if packet with parse error are not to be dropped */
-		err_cfg.errors |= DPNI_ERROR_PHE | DPNI_ERROR_BLE;
+		if (!(priv->flags & DPAA2_PARSE_ERR_DROP))
+			err_cfg.errors |= DPNI_ERROR_PHE | DPNI_ERROR_BLE;
 
 		err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE;
 	}
@@ -2909,6 +2911,12 @@ dpaa2_dev_init(struct rte_eth_dev *eth_dev)
 		DPAA2_PMD_INFO("Enable error queue");
 	}
 
+	/* Packets with parse error to be dropped in hw */
+	if (dpaa2_get_devargs(dev->devargs, DRIVER_RX_PARSE_ERR_DROP)) {
+		priv->flags |= DPAA2_PARSE_ERR_DROP;
+		DPAA2_PMD_INFO("Drop parse error packets in hw");
+	}
+
 	if (getenv("DPAA2_PRINT_RX_PARSER_RESULT"))
 		dpaa2_print_parser_result = 1;
 
@@ -3278,5 +3286,6 @@ RTE_PMD_REGISTER_PARAM_STRING(NET_DPAA2_PMD_DRIVER_NAME,
 		DRIVER_LOOPBACK_MODE "=<int> "
 		DRIVER_NO_PREFETCH_MODE "=<int>"
 		DRIVER_TX_CONF "=<int>"
+		DRIVER_RX_PARSE_ERR_DROP "=<int>"
 		DRIVER_ERROR_QUEUE "=<int>");
 RTE_LOG_REGISTER_DEFAULT(dpaa2_logtype_pmd, NOTICE);
diff --git a/drivers/net/dpaa2/dpaa2_ethdev.h b/drivers/net/dpaa2/dpaa2_ethdev.h
index f4adb76bb6..b2ab3d539b 100644
--- a/drivers/net/dpaa2/dpaa2_ethdev.h
+++ b/drivers/net/dpaa2/dpaa2_ethdev.h
@@ -70,6 +70,9 @@
  */
 #define DPAA2_TX_CGR_OFF	RTE_BIT32(0)
 
+/* Drop packets with parsing error in hw */
+#define DPAA2_PARSE_ERR_DROP	RTE_BIT32(1)
+
 /* Disable RX tail drop, default is enable */
 #define DPAA2_RX_TAILDROP_OFF	RTE_BIT32(2)
 
-- 
2.43.0

[PATCH 13/15] net/dpaa2: optimize to prefetch next parser result

[Prashant Gupta]

From: Jun Yang <jun.yang@nxp.com>

Prefetch next parser result for either VA or PA mode.
This prefetch doesn't perform on LX2160A.

Signed-off-by: Jun Yang <jun.yang@nxp.com>
---
 drivers/net/dpaa2/dpaa2_rxtx.c | 64 ++++++++++++++++------------------
 1 file changed, 30 insertions(+), 34 deletions(-)

diff --git a/drivers/net/dpaa2/dpaa2_rxtx.c b/drivers/net/dpaa2/dpaa2_rxtx.c
index 8f932be635..dcaa9203b3 100644
--- a/drivers/net/dpaa2/dpaa2_rxtx.c
+++ b/drivers/net/dpaa2/dpaa2_rxtx.c
@@ -520,6 +520,23 @@ eth_mbuf_to_sg_fd(struct rte_mbuf *mbuf,
 	return 0;
 }
 
+static inline void
+dpaa2_dev_prefetch_next_psr(const struct qbman_result *dq)
+{
+	const struct qbman_fd *fd;
+	const struct dpaa2_annot_hdr *annotation;
+	uint64_t annot_iova;
+
+	dq++;
+
+	fd = qbman_result_DQ_fd(dq);
+	annot_iova = DPAA2_GET_FD_ADDR(fd) + DPAA2_FD_PTA_SIZE;
+	annotation = DPAA2_IOVA_TO_VADDR(annot_iova);
+
+	/** Prefetch from word3 to parse next header.*/
+	rte_prefetch0(&annotation->word3);
+}
+
 static void
 eth_mbuf_to_fd(struct rte_mbuf *mbuf,
 	       struct qbman_fd *fd,
@@ -845,18 +862,11 @@ dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
 			if (unlikely((status & QBMAN_DQ_STAT_VALIDFRAME) == 0))
 				continue;
 		}
-		fd = qbman_result_DQ_fd(dq_storage);
-
-#ifndef RTE_LIBRTE_DPAA2_USE_PHYS_IOVA
-		if (dpaa2_svr_family != SVR_LX2160A) {
-			const struct qbman_fd *next_fd =
-				qbman_result_DQ_fd(dq_storage + 1);
-			/* Prefetch Annotation address for the parse results */
-			rte_prefetch0(DPAA2_IOVA_TO_VADDR((DPAA2_GET_FD_ADDR(
-				next_fd) + DPAA2_FD_PTA_SIZE + 16)));
-		}
-#endif
+		if (dpaa2_svr_family != SVR_LX2160A)
+			/** Packet type is parsed from FRC for LX2160A.*/
+			dpaa2_dev_prefetch_next_psr(dq_storage);
 
+		fd = qbman_result_DQ_fd(dq_storage);
 		if (unlikely(DPAA2_FD_GET_FORMAT(fd) == qbman_fd_sg))
 			bufs[num_rx] = eth_sg_fd_to_mbuf(fd, eth_data->port_id);
 		else
@@ -1059,22 +1069,11 @@ dpaa2_dev_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
 					QBMAN_DQ_STAT_VALIDFRAME) == 0))
 					continue;
 			}
-			fd = qbman_result_DQ_fd(dq_storage);
-
-#ifndef RTE_LIBRTE_DPAA2_USE_PHYS_IOVA
-			if (dpaa2_svr_family != SVR_LX2160A) {
-				const struct qbman_fd *next_fd =
-					qbman_result_DQ_fd(dq_storage + 1);
-
-				/* Prefetch Annotation address for the parse
-				 * results.
-				 */
-				rte_prefetch0((DPAA2_IOVA_TO_VADDR(
-					DPAA2_GET_FD_ADDR(next_fd) +
-					DPAA2_FD_PTA_SIZE + 16)));
-			}
-#endif
+			if (dpaa2_svr_family != SVR_LX2160A)
+				/** Packet type is parsed from FRC for LX2160A.*/
+				dpaa2_dev_prefetch_next_psr(dq_storage);
 
+			fd = qbman_result_DQ_fd(dq_storage);
 			if (unlikely(DPAA2_FD_GET_FORMAT(fd) == qbman_fd_sg))
 				bufs[num_rx] = eth_sg_fd_to_mbuf(fd,
 							eth_data->port_id);
@@ -1115,7 +1114,7 @@ uint16_t dpaa2_dev_tx_conf(void *queue)
 	int ret, num_tx_conf = 0, num_pulled;
 	uint8_t pending, status;
 	struct qbman_swp *swp;
-	const struct qbman_fd *fd, *next_fd;
+	const struct qbman_fd *fd;
 	struct qbman_pull_desc pulldesc;
 	struct qbman_release_desc releasedesc;
 	uint32_t bpid;
@@ -1183,14 +1182,11 @@ uint16_t dpaa2_dev_tx_conf(void *queue)
 					QBMAN_DQ_STAT_VALIDFRAME) == 0))
 					continue;
 			}
-			fd = qbman_result_DQ_fd(dq_storage);
-
-			next_fd = qbman_result_DQ_fd(dq_storage + 1);
-			/* Prefetch Annotation address for the parse results */
-			rte_prefetch0((void *)(size_t)
-				(DPAA2_GET_FD_ADDR(next_fd) +
-				 DPAA2_FD_PTA_SIZE + 16));
+			if (dpaa2_svr_family != SVR_LX2160A)
+				/** Packet type is parsed from FRC for LX2160A.*/
+				dpaa2_dev_prefetch_next_psr(dq_storage);
 
+			fd = qbman_result_DQ_fd(dq_storage);
 			bpid = DPAA2_GET_FD_BPID(fd);
 
 			/* Create a release descriptor required for releasing
-- 
2.43.0

[PATCH 14/15] net/dpaa2: add eCPRI header and message dump

[Prashant Gupta]

From: Jun Yang <jun.yang@nxp.com>

Dump ECPRI header over ethernet/vlan/udp.
Dump message contents according to various types.
ECPRI are set to parser result areas by softparser.

Signed-off-by: Jun Yang <jun.yang@nxp.com>
---
 drivers/net/dpaa2/dpaa2_parse_dump.h | 124 +++++++++++++++++++++++++++
 1 file changed, 124 insertions(+)

diff --git a/drivers/net/dpaa2/dpaa2_parse_dump.h b/drivers/net/dpaa2/dpaa2_parse_dump.h
index 78fd3b768c..bcab3bf0cb 100644
--- a/drivers/net/dpaa2/dpaa2_parse_dump.h
+++ b/drivers/net/dpaa2/dpaa2_parse_dump.h
@@ -74,6 +74,122 @@ struct dpaa2_fapr_field_info support_dump_fields[] = {
 	}
 };
 
+static inline void
+dpaa2_print_ecpri(struct dpaa2_fapr_array *fapr)
+{
+	uint8_t ecpri_type;
+	struct rte_ecpri_combined_msg_hdr ecpri_msg;
+
+	ecpri_type = fapr->pr[DPAA2_FAFE_PSR_OFFSET];
+	if ((ecpri_type >> 1) > 7) {
+		DPAA2_PR_PRINT("Invalid ECPRI type(0x%02x)\r\n",
+			ecpri_type);
+	} else {
+		DPAA2_PR_PRINT("ECPRI type %d present\r\n",
+			ecpri_type >> 1);
+		if (ecpri_type == ECPRI_FAFE_TYPE_0 ||
+			ecpri_type == ECPRI_FAFE_TYPE_1) {
+			/* Type 0 is identical to type1*/
+			ecpri_msg.type0.pc_id =
+				fapr->pr[DPAA2_ECPRI_MSG_OFFSET + 1];
+			ecpri_msg.type0.pc_id =
+				ecpri_msg.type0.pc_id << 8;
+			ecpri_msg.type0.pc_id |=
+				fapr->pr[DPAA2_ECPRI_MSG_OFFSET];
+
+			ecpri_msg.type0.seq_id =
+				fapr->pr[DPAA2_ECPRI_MSG_OFFSET + 3];
+			ecpri_msg.type0.seq_id =
+				ecpri_msg.type0.seq_id << 8;
+			ecpri_msg.type0.seq_id |=
+				fapr->pr[DPAA2_ECPRI_MSG_OFFSET + 2];
+
+			DPAA2_PR_PRINT("pc_id(0x%04x) seq_id(0x%04x)\r\n",
+				rte_be_to_cpu_16(ecpri_msg.type0.pc_id),
+				rte_be_to_cpu_16(ecpri_msg.type0.seq_id));
+		} else if (ecpri_type == ECPRI_FAFE_TYPE_2) {
+			ecpri_msg.type2.rtc_id =
+				fapr->pr[DPAA2_ECPRI_MSG_OFFSET + 1];
+			ecpri_msg.type2.rtc_id =
+				ecpri_msg.type2.rtc_id << 8;
+			ecpri_msg.type2.rtc_id |=
+				fapr->pr[DPAA2_ECPRI_MSG_OFFSET];
+
+			ecpri_msg.type2.seq_id =
+				fapr->pr[DPAA2_ECPRI_MSG_OFFSET + 3];
+			ecpri_msg.type2.seq_id =
+				ecpri_msg.type2.seq_id << 8;
+			ecpri_msg.type2.seq_id |=
+				fapr->pr[DPAA2_ECPRI_MSG_OFFSET + 2];
+
+			DPAA2_PR_PRINT("rtc_id(0x%04x) seq_id(0x%04x)\r\n",
+				rte_be_to_cpu_16(ecpri_msg.type2.rtc_id),
+				rte_be_to_cpu_16(ecpri_msg.type2.seq_id));
+		} else if (ecpri_type == ECPRI_FAFE_TYPE_3) {
+			DPAA2_PR_PRINT("ECPRI type3 extract not support\r\n");
+		} else if (ecpri_type == ECPRI_FAFE_TYPE_4) {
+			ecpri_msg.type4.rma_id =
+				fapr->pr[DPAA2_ECPRI_MSG_OFFSET];
+			ecpri_msg.type4.rw =
+				fapr->pr[DPAA2_ECPRI_MSG_OFFSET + 1] >> 4;
+			ecpri_msg.type4.rr =
+				fapr->pr[DPAA2_ECPRI_MSG_OFFSET + 1] & 0xf;
+
+			ecpri_msg.type4.ele_id =
+				fapr->pr[DPAA2_ECPRI_MSG_OFFSET + 3];
+			ecpri_msg.type4.ele_id =
+				ecpri_msg.type4.ele_id << 8;
+			ecpri_msg.type4.ele_id |=
+				fapr->pr[DPAA2_ECPRI_MSG_OFFSET + 2];
+
+			DPAA2_PR_PRINT("rma_id(0x%02x) rw(0x%02x)",
+				ecpri_msg.type4.rma_id, ecpri_msg.type4.rw);
+			DPAA2_PR_PRINT(" rr(0x%02x) ele_id(0x%04x)\r\n",
+				ecpri_msg.type4.rr,
+				rte_be_to_cpu_16(ecpri_msg.type4.ele_id));
+		} else if (ecpri_type == ECPRI_FAFE_TYPE_5) {
+			ecpri_msg.type5.msr_id =
+				fapr->pr[DPAA2_ECPRI_MSG_OFFSET];
+			ecpri_msg.type5.act_type =
+				fapr->pr[DPAA2_ECPRI_MSG_OFFSET + 1];
+
+			DPAA2_PR_PRINT("rma_id(0x%02x) rw(0x%02x)\r\n",
+				ecpri_msg.type5.msr_id,
+				ecpri_msg.type5.act_type);
+		} else if (ecpri_type == ECPRI_FAFE_TYPE_6) {
+			ecpri_msg.type6.rst_id =
+				fapr->pr[DPAA2_ECPRI_MSG_OFFSET + 1];
+			ecpri_msg.type6.rst_id =
+				ecpri_msg.type6.rst_id << 8;
+			ecpri_msg.type6.rst_id |=
+				fapr->pr[DPAA2_ECPRI_MSG_OFFSET];
+
+			ecpri_msg.type6.rst_op =
+				fapr->pr[DPAA2_ECPRI_MSG_OFFSET + 2];
+
+			DPAA2_PR_PRINT("rst_id(0x%04x) rst_op(0x%02x)\r\n",
+				rte_be_to_cpu_16(ecpri_msg.type6.rst_id),
+				ecpri_msg.type6.rst_op);
+		} else if (ecpri_type == ECPRI_FAFE_TYPE_7) {
+			ecpri_msg.type7.evt_id =
+				fapr->pr[DPAA2_ECPRI_MSG_OFFSET];
+			ecpri_msg.type7.evt_type =
+				fapr->pr[DPAA2_ECPRI_MSG_OFFSET + 1];
+			ecpri_msg.type7.seq =
+				fapr->pr[DPAA2_ECPRI_MSG_OFFSET + 2];
+			ecpri_msg.type7.number =
+				fapr->pr[DPAA2_ECPRI_MSG_OFFSET + 3];
+
+			DPAA2_PR_PRINT("evt_id(0x%02x) evt_type(0x%02x)",
+				ecpri_msg.type7.evt_id,
+				ecpri_msg.type7.evt_type);
+			DPAA2_PR_PRINT(" seq(0x%02x) number(0x%02x)\r\n",
+				ecpri_msg.type7.seq,
+				ecpri_msg.type7.number);
+		}
+	}
+}
+
 static inline void
 dpaa2_print_faf(struct dpaa2_fapr_array *fapr)
 {
@@ -82,6 +198,7 @@ dpaa2_print_faf(struct dpaa2_fapr_array *fapr)
 	int i, byte_pos, bit_pos, vxlan = 0, vxlan_vlan = 0;
 	struct rte_ether_hdr vxlan_in_eth;
 	uint16_t vxlan_vlan_tci;
+	int ecpri = 0;
 
 	for (i = 0; i < faf_bit_len; i++) {
 		faf_bits[i].position = i;
@@ -111,6 +228,8 @@ dpaa2_print_faf(struct dpaa2_fapr_array *fapr)
 			faf_bits[i].name = "UDP Present";
 		else if (i == FAF_TCP_FRAM)
 			faf_bits[i].name = "TCP Present";
+		else if (i == FAFE_ECPRI_FRAM)
+			faf_bits[i].name = "ECPRI Present";
 		else
 			faf_bits[i].name = "Check RM for this unusual frame";
 	}
@@ -124,6 +243,8 @@ dpaa2_print_faf(struct dpaa2_fapr_array *fapr)
 				faf_bits[i].position, faf_bits[i].name);
 			if (i == FAF_VXLAN_FRAM)
 				vxlan = 1;
+			else if (i == FAFE_ECPRI_FRAM)
+				ecpri = 1;
 		}
 	}
 
@@ -192,6 +313,9 @@ dpaa2_print_faf(struct dpaa2_fapr_array *fapr)
 				vxlan_vlan_tci);
 		}
 	}
+
+	if (ecpri)
+		dpaa2_print_ecpri(fapr);
 }
 
 static inline void
-- 
2.43.0

[PATCH 15/15] net/dpaa2: add Policer stats for each TC

[Prashant Gupta]

Add support of Policer stats for each TC.
Also dpmac stats are supported for MC version > 10.39.0

Signed-off-by: Prashant Gupta <prashant.gupta_3@nxp.com>
---
 drivers/net/dpaa2/dpaa2_ethdev.c | 117 ++++++++++++++++++++++++++-----
 1 file changed, 101 insertions(+), 16 deletions(-)

diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c
index 5b72243346..be86fcb853 100644
--- a/drivers/net/dpaa2/dpaa2_ethdev.c
+++ b/drivers/net/dpaa2/dpaa2_ethdev.c
@@ -104,6 +104,46 @@ static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = {
 	{"egress_confirmed_frames", 2, 4},
 	{"cgr_reject_frames", 4, 0},
 	{"cgr_reject_bytes", 4, 1},
+	{"TC_0_policer_cnt_red", 5, 0},
+	{"TC_0_policer_cnt_yellow", 5, 1},
+	{"TC_0_policer_cnt_green", 5, 2},
+	{"TC_0_policer_cnt_re_red", 5, 3},
+	{"TC_0_policer_cnt_re_yellow", 5, 4},
+	{"TC_1_policer_cnt_red", 6, 0},
+	{"TC_1_policer_cnt_yellow", 6, 1},
+	{"TC_1_policer_cnt_green", 6, 2},
+	{"TC_1_policer_cnt_re_red", 6, 3},
+	{"TC_1_policer_cnt_re_yellow", 6, 4},
+	{"TC_2_policer_cnt_red", 7, 0},
+	{"TC_2_policer_cnt_yellow", 7, 1},
+	{"TC_2_policer_cnt_green", 7, 2},
+	{"TC_2_policer_cnt_re_red", 7, 3},
+	{"TC_2_policer_cnt_re_yellow", 7, 4},
+	{"TC_3_policer_cnt_red", 8, 0},
+	{"TC_3_policer_cnt_yellow", 8, 1},
+	{"TC_3_policer_cnt_green", 8, 2},
+	{"TC_3_policer_cnt_re_red", 8, 3},
+	{"TC_3_policer_cnt_re_yellow", 8, 4},
+	{"TC_4_policer_cnt_red", 9, 0},
+	{"TC_4_policer_cnt_yellow", 9, 1},
+	{"TC_4_policer_cnt_green", 9, 2},
+	{"TC_4_policer_cnt_re_red", 9, 3},
+	{"TC_4_policer_cnt_re_yellow", 9, 4},
+	{"TC_5_policer_cnt_red", 10, 0},
+	{"TC_5_policer_cnt_yellow", 10, 1},
+	{"TC_5_policer_cnt_green", 10, 2},
+	{"TC_5_policer_cnt_re_red", 10, 3},
+	{"TC_5_policer_cnt_re_yellow", 10, 4},
+	{"TC_6_policer_cnt_red", 11, 0},
+	{"TC_6_policer_cnt_yellow", 11, 1},
+	{"TC_6_policer_cnt_green", 11, 2},
+	{"TC_6_policer_cnt_re_red", 11, 3},
+	{"TC_6_policer_cnt_re_yellow", 11, 4},
+	{"TC_7_policer_cnt_red", 12, 0},
+	{"TC_7_policer_cnt_yellow", 12, 1},
+	{"TC_7_policer_cnt_green", 12, 2},
+	{"TC_7_policer_cnt_re_red", 12, 3},
+	{"TC_7_policer_cnt_re_yellow", 12, 4},
 	{"mac_rx_64 bytes", 0, 0},
 	{"mac_rx_65-127 bytes", 0, 0},
 	{"mac_rx_128-255 bytes", 0, 0},
@@ -1841,6 +1881,11 @@ dpaa2_dev_mac_setup_stats(struct rte_eth_dev *dev)
 	priv->cnt_values_dma_mem = NULL;
 }
 
+/*
+ * dpaa2_dev_xstats_get(): Get counters of dpni and dpmac.
+ * MAC (mac_*) counters are supported on MC version > 10.39.0
+ * TC_x_policer_* counters are supported only when Policer is enable.
+ */
 static int
 dpaa2_dev_xstats_get(struct rte_eth_dev *dev,
 	struct rte_eth_xstat *xstats, unsigned int n)
@@ -1848,10 +1893,13 @@ dpaa2_dev_xstats_get(struct rte_eth_dev *dev,
 	struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
 	unsigned int i = 0, j = 0, num = RTE_DIM(dpaa2_xstats_strings);
 	struct dpaa2_dev_priv *priv = dev->data->dev_private;
-	union dpni_statistics value[5] = {};
+	union dpni_statistics value[13] = {};
+	struct mc_version mc_ver_info = {0};
+	struct dpni_rx_tc_policing_cfg cfg;
 	uint8_t page_id, stats_id;
 	uint64_t *cnt_values;
 	int32_t retcode;
+	int16_t tc;
 
 	if (n < num)
 		return num;
@@ -1888,6 +1936,27 @@ dpaa2_dev_xstats_get(struct rte_eth_dev *dev,
 			break;
 		}
 	}
+
+	for (tc = 0; tc < priv->num_rx_tc; tc++) {
+		retcode = dpni_get_rx_tc_policing(dpni, CMD_PRI_LOW,
+						  priv->token, tc,
+						  &cfg);
+		if (retcode) {
+			DPAA2_PMD_ERR("Error to get the policer rule: %d", retcode);
+			goto err;
+		}
+
+		/* get policer stats if policer is enabled */
+		if (cfg.mode != 0) {
+			/* Get Counters from page_5*/
+			retcode = dpni_get_statistics(dpni, CMD_PRI_LOW,
+						      priv->token, 5, tc,
+						      &value[(tc + 5)]);
+			if (retcode)
+				goto err;
+		}
+	}
+
 	while (i < (num - DPAA2_MAC_NUM_STATS)) {
 		xstats[i].id = i;
 		page_id = dpaa2_xstats_strings[i].page_id;
@@ -1896,29 +1965,45 @@ dpaa2_dev_xstats_get(struct rte_eth_dev *dev,
 		i++;
 	}
 
-	dpaa2_dev_mac_setup_stats(dev);
-	retcode = dpni_get_mac_statistics(dpni, CMD_PRI_LOW, priv->token,
-					  priv->cnt_idx_iova, priv->cnt_values_iova,
-					  DPAA2_MAC_NUM_STATS);
-	if (retcode) {
-		DPAA2_PMD_WARN("MAC (mac_*) counters are not supported!!");
+	if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info))
+		DPAA2_PMD_WARN("Unable to obtain MC version");
+
+	/* mac_statistics supported on MC version > 10.39.0 */
+	if (mc_ver_info.major >= MC_VER_MAJOR &&
+	    mc_ver_info.minor >= MC_VER_MINOR &&
+	    mc_ver_info.revision > 0) {
+		dpaa2_dev_mac_setup_stats(dev);
+		retcode = dpni_get_mac_statistics(dpni, CMD_PRI_LOW, priv->token,
+						  priv->cnt_idx_iova,
+						  priv->cnt_values_iova,
+						  DPAA2_MAC_NUM_STATS);
+		if (retcode) {
+			while (i >= (num - DPAA2_MAC_NUM_STATS) && i < num) {
+				xstats[i].id = i;
+				xstats[i].value = 0;
+				i++;
+			}
+		}
+		if (!retcode) {
+			cnt_values = priv->cnt_values_dma_mem;
+			while (i >= (num - DPAA2_MAC_NUM_STATS) && i < num) {
+				/* mac counters value */
+				xstats[i].id = i;
+				xstats[i].value = rte_le_to_cpu_64(*cnt_values++);
+				i++;
+			}
+		}
 		rte_free(priv->cnt_values_dma_mem);
 		rte_free(priv->cnt_idx_dma_mem);
+		priv->cnt_idx_dma_mem = NULL;
+		priv->cnt_values_dma_mem = NULL;
+	} else {
 		while (i >= (num - DPAA2_MAC_NUM_STATS) && i < num) {
 			xstats[i].id = i;
 			xstats[i].value = 0;
 			i++;
 		}
 	}
-	if (!retcode) {
-		cnt_values = priv->cnt_values_dma_mem;
-		while (i >= (num - DPAA2_MAC_NUM_STATS) && i < num) {
-			/* mac counters value */
-			xstats[i].id = i;
-			xstats[i].value = rte_le_to_cpu_64(*cnt_values++);
-			i++;
-		}
-	}
 
 	return i;
 err:
-- 
2.43.0