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(unknown [10.28.36.48]) by maili.marvell.com (Postfix) with ESMTP id 2E0523F708A; Thu, 19 Feb 2026 01:09:03 -0800 (PST) From: Rahul Bhansali To: , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Harman Kalra CC: , Rahul Bhansali Subject: [PATCH 4/8] common/cnxk: add RQ PB and WQE cache config Date: Thu, 19 Feb 2026 14:38:43 +0530 Message-ID: <20260219090847.3257753-4-rbhansali@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260219090847.3257753-1-rbhansali@marvell.com> References: <20260219090847.3257753-1-rbhansali@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Authority-Analysis: v=2.4 cv=T/GBjvKQ c=1 sm=1 tr=0 ts=6996d33e cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=HzLeVaNsDn8A:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=M5GUcnROAAAA:8 a=TA6KQb-nIjAiVJtrjLsA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjE5MDA4MyBTYWx0ZWRfX9XjYtc/u+YcK 1OS7V3Va7CgjwnpMAYCUDxrIdl8lJ312ZrzS70eGc78apga0ZbxLulBLrGIr/BOcBqpNePu+ARa Pugy59nSP93hblfXAAGgSC5QpLMOWFq5WyffeIEZqA/2Frdy+ll23BsTewnuusKTFXTH0y6Db9N +SvmvJQemFa/Rra9n90FfkutFT9amvw6HeTWlS3GSpsPIZwqI7UDOSj1bhE9HkJzr6AODRAV0w9 qRf0kuj8k5fzot51v2AEJd5C/N69mtRLpB4nNL9hAUTQN32U/9H0ufrTmHGB8ukEq2aY/RCM10k ci6IeKuXT4msetsp3140ixprXRYPsLPNEK6stq8AOBcbBr0UoiZQXmvFtiY92qW9WVJwnEzg9J9 wnh6mX0DrjqEokLRKQUMplHTrKX8ldzTXPgbEJD4d48spLWhyu48QX1nwuR81MMNv/ry7ZvJIh7 eCusof0LkcJks4SVTFQ== X-Proofpoint-ORIG-GUID: dkZC-TskWp244GG5RpDKv3LxM4phXmw3 X-Proofpoint-GUID: dkZC-TskWp244GG5RpDKv3LxM4phXmw3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-19_02,2026-02-18_01,2025-10-01_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Adds RQ's PB (Packet buffer) and WQE cache configuration options. Signed-off-by: Rahul Bhansali --- drivers/common/cnxk/roc_nix.h | 14 ++++++++++++++ drivers/common/cnxk/roc_nix_inl.c | 2 ++ drivers/common/cnxk/roc_nix_queue.c | 16 ++++++++-------- 3 files changed, 24 insertions(+), 8 deletions(-) diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index ffa1a706f9..7bc3e1f5c6 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -34,6 +34,16 @@ #define ROC_NIX_LSO_FORMAT_IDX_TSOV6 1 #define ROC_NIX_LSO_FORMAT_IDX_IPV4 2 +#define ROC_NIX_RQ_MAX_PB_CACHING_VAL 3 + +/* First aligned cache block is allocated into the LLC. + * All remaining cache blocks are not allocated. + */ +#define ROC_NIX_RQ_DEFAULT_PB_CACHING 2 + +/* Writes of WQE data are allocated into LLC. */ +#define ROC_NIX_RQ_DEFAULT_WQE_CACHING 1 + enum roc_nix_rss_reta_sz { ROC_NIX_RSS_RETA_SZ_64 = 64, ROC_NIX_RSS_RETA_SZ_128 = 128, @@ -448,6 +458,10 @@ struct roc_nix_rq { bool spb_drop_ena; /* XQE drop enable */ bool xqe_drop_ena; + /* RQ PB caching */ + uint8_t pb_caching; + /* RQ WQE caching */ + uint8_t wqe_caching; /* End of Input parameters */ struct roc_nix *roc_nix; uint64_t meta_aura_handle; diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index a21c40acf1..911c349604 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -1838,6 +1838,8 @@ roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq, bool enable) inl_rq->spb_ena = rq->spb_ena; inl_rq->spb_aura_handle = rq->spb_aura_handle; inl_rq->spb_size = rq->spb_size; + inl_rq->pb_caching = rq->pb_caching; + inl_rq->wqe_caching = rq->wqe_caching; if (roc_errata_nix_no_meta_aura()) { uint64_t aura_limit = diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c index ab3a71ec60..ef9b651022 100644 --- a/drivers/common/cnxk/roc_nix_queue.c +++ b/drivers/common/cnxk/roc_nix_queue.c @@ -499,7 +499,7 @@ nix_rq_cn9k_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, aq->rq.sso_grp = rq->hwgrp; aq->rq.ena_wqwd = 1; aq->rq.wqe_skip = rq->wqe_skip; - aq->rq.wqe_caching = 1; + aq->rq.wqe_caching = rq->wqe_caching; aq->rq.good_utag = rq->tag_mask >> 24; aq->rq.bad_utag = rq->tag_mask >> 24; @@ -530,7 +530,7 @@ nix_rq_cn9k_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, aq->rq.lpb_sizem1 = rq->lpb_size / 8; aq->rq.lpb_sizem1 -= 1; /* Expressed in size minus one */ aq->rq.ena = ena; - aq->rq.pb_caching = 0x2; /* First cache aligned block to LLC */ + aq->rq.pb_caching = rq->pb_caching; aq->rq.xqe_imm_size = 0; /* No pkt data copy to CQE */ aq->rq.rq_int_ena = 0; /* Many to one reduction */ @@ -616,7 +616,7 @@ nix_rq_cn10k_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cf aq->rq.sso_grp = rq->hwgrp; aq->rq.ena_wqwd = 1; aq->rq.wqe_skip = rq->wqe_skip; - aq->rq.wqe_caching = 1; + aq->rq.wqe_caching = rq->wqe_caching; aq->rq.xqe_drop_ena = 0; aq->rq.good_utag = rq->tag_mask >> 24; @@ -647,7 +647,7 @@ nix_rq_cn10k_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cf aq->rq.ipsecd_drop_en = 1; aq->rq.ena_wqwd = 1; aq->rq.wqe_skip = rq->wqe_skip; - aq->rq.wqe_caching = 1; + aq->rq.wqe_caching = rq->wqe_caching; } aq->rq.lpb_aura = roc_npa_aura_handle_to_aura(rq->aura_handle); @@ -683,7 +683,7 @@ nix_rq_cn10k_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cf aq->rq.spb_ena = 0; } - aq->rq.pb_caching = 0x2; /* First cache aligned block to LLC */ + aq->rq.pb_caching = rq->pb_caching; aq->rq.xqe_imm_size = 0; /* No pkt data copy to CQE */ aq->rq.rq_int_ena = 0; /* Many to one reduction */ @@ -797,7 +797,7 @@ nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg, boo aq->rq.sso_grp = rq->hwgrp; aq->rq.ena_wqwd = 1; aq->rq.wqe_skip = rq->wqe_skip; - aq->rq.wqe_caching = 1; + aq->rq.wqe_caching = rq->wqe_caching; aq->rq.good_utag = rq->tag_mask >> 24; aq->rq.bad_utag = rq->tag_mask >> 24; @@ -816,7 +816,7 @@ nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg, boo aq->rq.ipsecd_drop_en = 1; aq->rq.ena_wqwd = 1; aq->rq.wqe_skip = rq->wqe_skip; - aq->rq.wqe_caching = 1; + aq->rq.wqe_caching = rq->wqe_caching; } aq->rq.lpb_aura = roc_npa_aura_handle_to_aura(rq->aura_handle); @@ -852,7 +852,7 @@ nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg, boo aq->rq.spb_ena = 0; } - aq->rq.pb_caching = 0x2; /* First cache aligned block to LLC */ + aq->rq.pb_caching = rq->pb_caching; aq->rq.xqe_imm_size = 0; /* No pkt data copy to CQE */ aq->rq.rq_int_ena = 0; /* Many to one reduction */ -- 2.34.1