RE: [PATCH v4 03/10] common/mlx5: extend SQ modify to support rate limit update

Slava Ovsiienko
2026-03-23T12:59:36Z

Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

> -----Original Message-----
> From: Vincent Jardin <vjardin@free.fr>
> Sent: Sunday, March 22, 2026 3:46 PM
> To: dev@dpdk.org
> Cc: Raslan Darawsheh <rasland@nvidia.com>; NBU-Contact-Thomas Monjalon
> (EXTERNAL) <thomas@monjalon.net>; andrew.rybchenko@oktetlabs.ru;
> Dariusz Sosnowski <dsosnowski@nvidia.com>; Slava Ovsiienko
> <viacheslavo@nvidia.com>; Bing Zhao <bingz@nvidia.com>; Ori Kam
> <orika@nvidia.com>; Suanming Mou <suanmingm@nvidia.com>; Matan Azrad
> <matan@nvidia.com>; stephen@networkplumber.org;
> aman.deep.singh@intel.com; Vincent Jardin <vjardin@free.fr>
> Subject: [PATCH v4 03/10] common/mlx5: extend SQ modify to support rate
> limit update
>
> Add rl_update and packet_pacing_rate_limit_index fields to
> mlx5_devx_modify_sq_attr. When rl_update is set, the modify SQ command
> sets modify_bitmask bit 0 and writes the PP index into the SQ context, allowing
> dynamic rate changes on a live RDY SQ without teardown.
>
> modify_sq_in.modify_bitmask[0x40] bit 0 controls the
> packet_pacing_rate_limit_index.
>
> Supported hardware:
> - ConnectX-6 Dx: per-SQ rate via packet_pacing_rate_limit_index
> - ConnectX-7/8: same SQ context field, also supports wait-on-time
> - BlueField-2/3: same modify_sq command support
>
> Not supported:
> - ConnectX-5: supports packet_pacing but only at SQ creation time,
> dynamic modify_bitmask update may not be supported on all FW
> - ConnectX-4 Lx and earlier: no packet_pacing support
>
> Signed-off-by: Vincent Jardin <vjardin@free.fr>
> ---
> drivers/common/mlx5/mlx5_devx_cmds.c | 8 ++++++++
> drivers/common/mlx5/mlx5_devx_cmds.h | 3 +++
> drivers/common/mlx5/mlx5_prm.h | 7 +++++++
> 3 files changed, 18 insertions(+)
>
> diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c
> b/drivers/common/mlx5/mlx5_devx_cmds.c
> index 8f53303fa7..102f84fd5c 100644
> --- a/drivers/common/mlx5/mlx5_devx_cmds.c
> +++ b/drivers/common/mlx5/mlx5_devx_cmds.c
> @@ -2129,6 +2129,14 @@ mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj
> *sq,
> MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
> MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq);
> MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr-
> >hairpin_peer_vhca);
> + if (sq_attr->rl_update) {
> + uint64_t msk = MLX5_GET64(modify_sq_in, in,
> modify_bitmask);
> +
> + msk |=
> MLX5_MODIFY_SQ_IN_MODIFY_BITMASK_PACKET_PACING_RATE_LIMIT_IND
> EX;
> + MLX5_SET64(modify_sq_in, in, modify_bitmask, msk);
> + MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,
> + sq_attr->packet_pacing_rate_limit_index);
> + }
> ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in),
> out, sizeof(out));
> if (ret) {
> diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h
> b/drivers/common/mlx5/mlx5_devx_cmds.h
> index 930ae2c072..82d949972b 100644
> --- a/drivers/common/mlx5/mlx5_devx_cmds.h
> +++ b/drivers/common/mlx5/mlx5_devx_cmds.h
> @@ -519,6 +519,9 @@ struct mlx5_devx_modify_sq_attr {
> uint32_t state:4;
> uint32_t hairpin_peer_rq:24;
> uint32_t hairpin_peer_vhca:16;
> + uint32_t rl_update:1;
> + /* Set to update packet_pacing_rate_limit_index on a live SQ. */
> + uint32_t packet_pacing_rate_limit_index:16;
> };
>
>
> diff --git a/drivers/common/mlx5/mlx5_prm.h
> b/drivers/common/mlx5/mlx5_prm.h index ba33336e58..597d06362f 100644
> --- a/drivers/common/mlx5/mlx5_prm.h
> +++ b/drivers/common/mlx5/mlx5_prm.h
> @@ -2985,6 +2985,7 @@ struct mlx5_ifc_create_tis_in_bits {
> struct mlx5_ifc_tisc_bits ctx;
> };
>
> +/* Bits for modify_rq_in.modify_bitmask (Receive Queue). */
> enum {
> MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM = 1ULL << 0,
> MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, @@ -
> 2992,6 +2993,12 @@ enum {
> MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID =
> 1ULL << 3, };
>
> +/* Bits for modify_sq_in.modify_bitmask (Send Queue). */ enum {
> +
> MLX5_MODIFY_SQ_IN_MODIFY_BITMASK_PACKET_PACING_RATE_LI
> MIT_INDEX =
> + 1ULL << 0,
> +};
> +
> struct mlx5_ifc_modify_rq_in_bits {
> u8 opcode[0x10];
> u8 uid[0x10];
> --
> 2.43.0