[PATCH] net/mlx5: fix VLAN strip info for CQE compression

[PATCH] net/mlx5: fix VLAN strip info for CQE compression

[Dariusz Sosnowski]

When L3/L4 mini CQE format is used with CQE compression
(rxq_cqe_comp_en set to 4 in lower 3 bits),
each mini CQE reports packet header info for relevant packet.
One bit in that header info is dedicated to CVLAN info,
used to determine whether CVLAN is present in the received packet.
This info is used to determine VLAN stripping info
when relevant offload is enabled.

Before this patch, users might have seen incorrectly set/unset
RTE_MBUF_F_RX_VLAN and RTE_MBUF_F_RX_VLAN_STRIPPED flags because:

- Struct for mlx5 mini CQE incorrectly defined the location
  of packet header info byte - it was swapped with neighboring
  reserved byte.
- CVLAN bit was checked incorrectly because of cast to uint16_t
  and big endian change. It should be checked as uint8_t.

This patch addresses the above.

Fixes: 54c2d46b160f ("net/mlx5: support flow tag and packet header miniCQEs")
Cc: akozyrev@nvidia.com
Cc: stable@dpdk.org

Signed-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
---
 drivers/common/mlx5/mlx5_prm.h | 2 +-
 drivers/net/mlx5/mlx5_rx.c     | 3 +--
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index ba33336e58..11b14e4f9d 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -5516,8 +5516,8 @@ struct mlx5_mini_cqe8 {
 				uint16_t checksum;
 				uint16_t flow_tag_high;
 				struct {
-					uint8_t reserved;
 					uint8_t hdr_type;
+					uint8_t reserved;
 				};
 			};
 			uint16_t stride_idx;
diff --git a/drivers/net/mlx5/mlx5_rx.c b/drivers/net/mlx5/mlx5_rx.c
index bc0470e6af..da871fd18a 100644
--- a/drivers/net/mlx5/mlx5_rx.c
+++ b/drivers/net/mlx5/mlx5_rx.c
@@ -1000,8 +1000,7 @@ rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
 			vlan_strip = cqe->hdr_type_etc &
 				     RTE_BE16(MLX5_CQE_VLAN_STRIPPED);
 		else
-			vlan_strip = mcqe->hdr_type &
-				     RTE_BE16(MLX5_CQE_VLAN_STRIPPED);
+			vlan_strip = mcqe->hdr_type & MLX5_CQE_VLAN_STRIPPED;
 		if (vlan_strip) {
 			pkt->ol_flags |= RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED;
 			pkt->vlan_tci = rte_be_to_cpu_16(cqe->vlan_info);
-- 
2.47.3

Re: [PATCH] net/mlx5: fix VLAN strip info for CQE compression

[Raslan Darawsheh]

Hi,


On 20/03/2026 6:00 PM, Dariusz Sosnowski wrote:
> When L3/L4 mini CQE format is used with CQE compression
> (rxq_cqe_comp_en set to 4 in lower 3 bits),
> each mini CQE reports packet header info for relevant packet.
> One bit in that header info is dedicated to CVLAN info,
> used to determine whether CVLAN is present in the received packet.
> This info is used to determine VLAN stripping info
> when relevant offload is enabled.
> 
> Before this patch, users might have seen incorrectly set/unset
> RTE_MBUF_F_RX_VLAN and RTE_MBUF_F_RX_VLAN_STRIPPED flags because:
> 
> - Struct for mlx5 mini CQE incorrectly defined the location
>    of packet header info byte - it was swapped with neighboring
>    reserved byte.
> - CVLAN bit was checked incorrectly because of cast to uint16_t
>    and big endian change. It should be checked as uint8_t.
> 
> This patch addresses the above.
> 
> Fixes: 54c2d46b160f ("net/mlx5: support flow tag and packet header miniCQEs")
> Cc: akozyrev@nvidia.com
> Cc: stable@dpdk.org
> 
> Signed-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
> ---

Patch applied to next-net-mlx,

Kindest regards
Raslan Darawsheh