[PATCH] net/mlx5: fix NAT64 HW registers calculation

[Bing Zhao <bingz@nvidia.com>]

mlx5 PMD needs to select a set of 3 HW registers
which will be used to implement NAT64 flow action.
For compatibility reasons one of these registers has to be REG_C_6.
Offending patch introduced a bug to register selection logic.
If REG_C_6 was not available for use,
no registers were selected for NAT64.
So all the registers' information would not be initialized for the
temporary storage of headers information of NAT64.

This patch adds missing logic to use the last 3 available tag registers
in this case, allowing NAT64 flow action to be used.

Fixes: f15535128617 ("net/mlx5: fix NAT64 register selection")
Cc: dsosnowski@nvidia.com
Cc: stable@dpdk.org

Signed-off-by: Bing Zhao <bingz@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
---
 drivers/net/mlx5/mlx5.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c
index d9bc5ee197..70f52df78a 100644
--- a/drivers/net/mlx5/mlx5.c
+++ b/drivers/net/mlx5/mlx5.c
@@ -1679,6 +1679,12 @@ mlx5_init_hws_flow_tags_registers(struct mlx5_dev_ctx_shared *sh)
 		reg->nat64_regs[0] = REG_C_6;
 		reg->nat64_regs[1] = reg->hw_avl_tags[j - 2];
 		reg->nat64_regs[2] = reg->hw_avl_tags[j - 1];
+	} else {
+		if (j >= MLX5_FLOW_NAT64_REGS_MAX) {
+			reg->nat64_regs[0] = reg->hw_avl_tags[j - 3];
+			reg->nat64_regs[1] = reg->hw_avl_tags[j - 2];
+			reg->nat64_regs[2] = reg->hw_avl_tags[j - 1];
+		}
 	}
 }
 
-- 
2.34.1