[PATCH v1 1/4] net/axgbe: fix MAC TCR speed select field width

[PATCH v1 1/4] net/axgbe: fix MAC TCR speed select field width

[Ashok Kumar Natarajan]

The MAC Transmit Configuration Register (TCR) speed select (SS)
field is defined as 2 bits wide, while the hardware specification
defines this field as 3 bits to encode all supported MAC speeds.

Update the SS field width to 3 bits to match the hardware
specification and avoid truncation of speed select values.

Fixes: 69e209be5464 ("net/axgbe: add register map and related macros")
Cc: stable@dpdk.org

Signed-off-by: Ashok Kumar Natarajan <ashokkumar.natarajan@amd.com>
---
 drivers/net/axgbe/axgbe_common.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index 0bceff5774..842077d972 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -492,7 +492,7 @@
 #define MAC_SSIR_SSINC_INDEX		16
 #define MAC_SSIR_SSINC_WIDTH		8
 #define MAC_TCR_SS_INDEX		29
-#define MAC_TCR_SS_WIDTH		2
+#define MAC_TCR_SS_WIDTH		3
 #define MAC_TCR_TE_INDEX		0
 #define MAC_TCR_TE_WIDTH		1
 #define MAC_TSCR_AV8021ASMEN_INDEX	28
-- 
2.34.1

[PATCH v1 2/4] net/axgbe: add 100 Mbps MAC speed select

[Ashok Kumar Natarajan]

SPEED_100 is not handled, leaving the MAC speed select unprogrammed
when a 100 Mbps link is used.

Add the required speed select (SS) encoding so the MAC is configured
according to the hardware specification for 100 Mbps operation.

Fixes: a5c7273771e8 ("net/axgbe: add phy programming APIs")
Cc: stable@dpdk.org

Signed-off-by: Ashok Kumar Natarajan <ashokkumar.natarajan@amd.com>
---
 drivers/net/axgbe/axgbe_dev.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/net/axgbe/axgbe_dev.c b/drivers/net/axgbe/axgbe_dev.c
index 10a99aeac2..482d3d8062 100644
--- a/drivers/net/axgbe/axgbe_dev.c
+++ b/drivers/net/axgbe/axgbe_dev.c
@@ -303,6 +303,9 @@ static int axgbe_set_speed(struct axgbe_port *pdata, int speed)
 	case SPEED_10:
 		ss = 0x07;
 		break;
+	case SPEED_100:
+		ss = 0x04;
+		break;
 	case SPEED_1000:
 		ss = 0x03;
 		break;
-- 
2.34.1

[PATCH v1 3/4] net/axgbe: fix auto-neg advert/supported defs

[Ashok Kumar Natarajan]

This patch corrects the auto‑negotiation advertised and supported
macro definitions in the axgbe driver. The previous mappings did not
properly reflect the PHY capabilities, leading to incorrect feature
advertisement and negotiation behavior. The updated macros ensure
accurate reporting and alignment with valid link modes.

Fixes: 562825a03435 ("net/axgbe: add phy register map and helper macros")
Cc: stable@dpdk.org

Signed-off-by: Ashok Kumar Natarajan <ashokkumar.natarajan@amd.com>
---
 drivers/net/axgbe/axgbe_phy.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/net/axgbe/axgbe_phy.h b/drivers/net/axgbe/axgbe_phy.h
index 1bedd8e132..e5568cce5f 100644
--- a/drivers/net/axgbe/axgbe_phy.h
+++ b/drivers/net/axgbe/axgbe_phy.h
@@ -211,7 +211,7 @@
 #define ADVERTISED_1000baseKX_Full	(1 << 17)
 #define ADVERTISED_1000baseT_Full	(1 << 5)
 #define ADVERTISED_100baseT_Full	(1 << 3)
-#define ADVERTISED_10baseT_Full		(1 << 2)
+#define ADVERTISED_10baseT_Full		(1 << 1)
 #define ADVERTISED_TP			(1 << 7)
 #define ADVERTISED_FIBRE		(1 << 10)
 #define ADVERTISED_Backplane            (1 << 16)
@@ -219,8 +219,8 @@
 #define SUPPORTED_1000baseKX_Full       (1 << 17)
 #define SUPPORTED_10000baseKR_Full      (1 << 19)
 #define SUPPORTED_2500baseX_Full	(1 << 15)
-#define SUPPORTED_10baseT_Full		(1 << 3)
-#define SUPPORTED_100baseT_Full         (1 << 2)
+#define SUPPORTED_10baseT_Full		(1 << 1)
+#define SUPPORTED_100baseT_Full         (1 << 3)
 #define SUPPORTED_1000baseT_Full        (1 << 5)
 #define SUPPORTED_10000baseT_Full       (1 << 12)
 #define SUPPORTED_2500baseX_Full        (1 << 15)
-- 
2.34.1

[PATCH v1 4/4] net/axgbe: fix SGMII autoneg status bits

[Ashok Kumar Natarajan]

The SGMII autonegotiation status bit definitions do not match the
hardware specification. The link status and duplex bits are defined
at incorrect positions, which can lead to incorrect link state and
duplex reporting.

Correct the SGMII autoneg status bit definitions to align with the
hardware specification.

Fixes: 572890ef6625 ("net/axgbe: add structs for MAC init and reset")
Cc: stable@dpdk.org

Signed-off-by: Ashok Kumar Natarajan <ashokkumar.natarajan@amd.com>
---
 drivers/net/axgbe/axgbe_ethdev.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/axgbe/axgbe_ethdev.h b/drivers/net/axgbe/axgbe_ethdev.h
index 24336f31f6..77c21469a8 100644
--- a/drivers/net/axgbe/axgbe_ethdev.h
+++ b/drivers/net/axgbe/axgbe_ethdev.h
@@ -114,12 +114,12 @@
 #define AXGBE_LINK_TIMEOUT		5
 #define AXGBE_KR_TRAINING_WAIT_ITER	50
 
-#define AXGBE_SGMII_AN_LINK_STATUS	BIT(1)
+#define AXGBE_SGMII_AN_LINK_STATUS	BIT(4)
 #define AXGBE_SGMII_AN_LINK_SPEED	(BIT(2) | BIT(3))
 #define AXGBE_SGMII_AN_LINK_SPEED_10	0x00
 #define AXGBE_SGMII_AN_LINK_SPEED_100	0x04
 #define AXGBE_SGMII_AN_LINK_SPEED_1000	0x08
-#define AXGBE_SGMII_AN_LINK_DUPLEX	BIT(4)
+#define AXGBE_SGMII_AN_LINK_DUPLEX	BIT(1)
 
 /* ECC correctable error notification window (seconds) */
 #define AXGBE_ECC_LIMIT			60
-- 
2.34.1

Re: [PATCH v1 1/4] net/axgbe: fix MAC TCR speed select field width

[Stephen Hemminger]

On Fri, 27 Mar 2026 17:50:03 +0530
Ashok Kumar Natarajan <ashokkumar.natarajan@amd.com> wrote:

> The MAC Transmit Configuration Register (TCR) speed select (SS)
> field is defined as 2 bits wide, while the hardware specification
> defines this field as 3 bits to encode all supported MAC speeds.
> 
> Update the SS field width to 3 bits to match the hardware
> specification and avoid truncation of speed select values.
> 
> Fixes: 69e209be5464 ("net/axgbe: add register map and related macros")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Ashok Kumar Natarajan <ashokkumar.natarajan@amd.com>
> ---

Applied to next-net