This series introduces a topology library that groups DPDK lcores based on
CPU cache hierarchy and NUMA topology. The goal is to provide a stable and
explicit API that allows applications to select lcores with better locality
and cache sharing characteristics.

The series includes:
  - EAL support for topology discovery using hwloc and domain-based lcore
    grouping (L1/L2/L3/L4/NUMA)
  - Topology-aware test cases validating API behavior and edge conditions
  - Programmer’s guide describing the topology library and APIs

The API is marked experimental and does not change existing lcore behavior
unless explicitly used by the application.

Changes in v5:
  - Addressed review comments from v4
  - Fixed ARM cross-compilation issues
  - Cleaned up domain iteration and error handling
  - Updated tests to cover domain edge cases
  - Documentation refinements and API usage clarification

Changes in v4:
  - Corrected domain selection semantics
  - Updated example usage
  - Fixed naming and typo issues

Changes in v3:
  - Fixed macro naming (USE_NO_TOPOLOGY)
  - Minor cleanups based on early feedback

Tested on:
  - AMD EPYC (Milan, Genoa, Siena, Turin, Turin-Dense, Sorano)
  - Intel Xeon (SPR-SP, GNR-SP)
  - ARM Ampere
  - NVIDIA Grace Superchip

Dependencies:
  - hwloc-dev (tested with 2.10.0)

Patch breakdown:
  1/3 eal/topology: add topology grouping for lcores
  2/3 app: add topology-aware test cases
  3/3 doc: add topology library documentation

Future Work:
 - integrate into examples
  -- hellowrld: ready
  -- pkt-distributor: in-progress
  -- l2fwd: ready
  -- l3fwd: to start
  -- eventdevpipeline: PoC ready
 - integrate topology test
  -- crypto: yet to start
  -- compression: yet to start
  -- dma: PoC ready
 - add new features for
  -- PQoS: yet to start
  -- Data Injection: PoC with BRDCM Thor-2 ready

Tested OS: Linux only, need help with BSD and Windows

Tested with and without hwloc-dev library for
 - Ampere, aarch64, Neoverse-N1, NUMA-2, 256 CPU threads
 - Grace superchip, aarch64, Neoverse-V2, NUMA-2, 144 CPU threads
 - Intel GNR-SP, 6767P, NUMA-2, 256 Threads
 - AMD EPYC Siena, 8534P, NUMA-1, 128 Threads
 - AMD EPYC Sorano, 8635P, NUMA-1, 168 Threads

Signed-off-by: Vipin Varghese <vipin.varghese@amd.com>
``

Vipin Varghese (3):
  eal/topology: add Topology grouping for lcores
  app: add topology aware test case
  doc: add new section topology

 app/test/meson.build                   |   1 +
 app/test/test_ring_perf.c              | 416 +++++++++++++-
 app/test/test_stack_perf.c             | 409 ++++++++++++++
 app/test/test_topology.c               | 676 ++++++++++++++++++++++
 config/meson.build                     |  18 +
 doc/api/doxy-api-index.md              |   1 +
 doc/guides/prog_guide/index.rst        |   3 +-
 doc/guides/prog_guide/topology_lib.rst | 155 +++++
 lib/eal/common/eal_private.h           |  74 +++
 lib/eal/common/eal_topology.c          | 747 +++++++++++++++++++++++++
 lib/eal/common/meson.build             |   1 +
 lib/eal/freebsd/eal.c                  |  10 +-
 lib/eal/include/meson.build            |   1 +
 lib/eal/include/rte_topology.h         | 255 +++++++++
 lib/eal/linux/eal.c                    |   7 +
 lib/eal/meson.build                    |   4 +
 16 files changed, 2773 insertions(+), 5 deletions(-)
 create mode 100644 app/test/test_topology.c
 create mode 100644 doc/guides/prog_guide/topology_lib.rst
 create mode 100644 lib/eal/common/eal_topology.c
 create mode 100644 lib/eal/include/rte_topology.h

-- 
2.43.0