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[204.195.96.226]) by smtp.gmail.com with ESMTPSA id 00721157ae682-8025c96ffd5sm6045897b3.9.2026.06.19.19.32.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Jun 2026 19:32:05 -0700 (PDT) From: Stephen Hemminger To: dev@dpdk.org Cc: Stephen Hemminger , Jiawen Wu , Zaiyu Wang Subject: [PATCH v5 20/24] net/txgbe: replace rte_atomic32 with stdatomic Date: Fri, 19 Jun 2026 19:28:45 -0700 Message-ID: <20260620023134.42877-21-stephen@networkplumber.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260620023134.42877-1-stephen@networkplumber.org> References: <20260620023134.42877-1-stephen@networkplumber.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The swfw_busy flag guarding the AML SW-FW mailbox is a one-bit lock, so convert it to RTE_ATOMIC(bool) and replace the legacy test-and-set / clear pair with explicit acquire-release: rte_atomic32_test_and_set -> rte_atomic_exchange_explicit(.., true, acquire) rte_atomic32_clear -> rte_atomic_store_explicit(.., false, release) Acquire on the take pairs with release on the drop, so accesses inside the critical section are synchronized between successive holders. Default zero-initialization of struct txgbe_hw still gives swfw_busy = false, so no init site needs updating. Note: The previous rte_atomic32_test_and_set return value was inverted relative to what this code expected; this patch incidentally corrects that. A standalone Fixes: patch is queued in net-next. Signed-off-by: Stephen Hemminger --- drivers/net/txgbe/base/txgbe_mng.c | 4 ++-- drivers/net/txgbe/base/txgbe_type.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/txgbe/base/txgbe_mng.c b/drivers/net/txgbe/base/txgbe_mng.c index a1974820b6..c58e1d6589 100644 --- a/drivers/net/txgbe/base/txgbe_mng.c +++ b/drivers/net/txgbe/base/txgbe_mng.c @@ -185,7 +185,7 @@ txgbe_host_interface_command_aml(struct txgbe_hw *hw, u32 *buffer, } /* try to get lock */ - while (rte_atomic32_test_and_set(&hw->swfw_busy)) { + while (rte_atomic_exchange_explicit(&hw->swfw_busy, true, rte_memory_order_acquire)) { timeout--; if (!timeout) return TXGBE_ERR_TIMEOUT; @@ -266,7 +266,7 @@ txgbe_host_interface_command_aml(struct txgbe_hw *hw, u32 *buffer, /* index++, index replace txgbe_hic_hdr.checksum */ hw->swfw_index = resp->index == TXGBE_HIC_HDR_INDEX_MAX ? 0 : resp->index + 1; - rte_atomic32_clear(&hw->swfw_busy); + rte_atomic_store_explicit(&hw->swfw_busy, false, rte_memory_order_release); return err; } diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h index ede780321f..d3c82d51a4 100644 --- a/drivers/net/txgbe/base/txgbe_type.h +++ b/drivers/net/txgbe/base/txgbe_type.h @@ -880,7 +880,7 @@ struct txgbe_hw { rte_spinlock_t phy_lock; /*amlite: new SW-FW mbox */ u8 swfw_index; - rte_atomic32_t swfw_busy; + RTE_ATOMIC(bool) swfw_busy; u32 fec_mode; u32 cur_fec_link; }; -- 2.53.0