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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by SA2PEPF000015CB.mail.protection.outlook.com (10.167.241.201) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.245.5 via Frontend Transport; Tue, 21 Jul 2026 12:14:16 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 21 Jul 2026 05:13:58 -0700 Received: from nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 21 Jul 2026 05:13:55 -0700 From: Viacheslav Ovsiienko To: CC: , , , , Subject: [PATCH] common/mlx5: fix overlapping memory ranges Date: Tue, 21 Jul 2026 15:13:37 +0300 Message-ID: <20260721121337.1608660-1-viacheslavo@nvidia.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015CB:EE_|SA1PR12MB8946:EE_ X-MS-Office365-Filtering-Correlation-Id: 1bb722a5-aafb-421a-dcc3-08dee72195fb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015CB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8946 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The mlx5 driver requires special objects named Memory Regions (MR) to perform DMA operations with network data. The memory pool(s) is used to provide memory and to cover pool addresses the mlx5 PMD -pre-creates the appropriate MRs on Rx queue creation. The pool memory can be non-contigous and split into segments. The PMD created MRs on the page alignment segment boundaries and it could cause the overlapping MRs (in case if the end address of one segmend is aligned to ceiling and the next segment start address is aligned to the floor). The MRs overlapping could cause the wrong MR fetching from the cache for the mbufs in the overlapping area if the starting mbuf address falls into overlapped area and raise the hardware memory protection exception. Fixes: 690b2a88c2f7 ("common/mlx5: add mempool registration facilities") Cc: stable@dpdk.org Signed-off-by: Viacheslav Ovsiienko Acked-by: Dariusz Sosnowski --- drivers/common/mlx5/mlx5_common_mr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/common/mlx5/mlx5_common_mr.c b/drivers/common/mlx5/mlx5_common_mr.c index aa2d5e88a4..e968e928a1 100644 --- a/drivers/common/mlx5/mlx5_common_mr.c +++ b/drivers/common/mlx5/mlx5_common_mr.c @@ -1504,7 +1504,7 @@ mlx5_get_mempool_ranges(struct rte_mempool *mp, bool is_extmem, qsort(chunks, chunks_n, sizeof(chunks[0]), mlx5_range_compare_start); contig_n = 1; for (i = 1; i < chunks_n; i++) - if (chunks[i - 1].end != chunks[i].start) { + if (chunks[i - 1].end < chunks[i].start) { chunks[contig_n - 1].end = chunks[i - 1].end; chunks[contig_n] = chunks[i]; contig_n++; -- 2.34.1