From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09A06C5B572 for ; Wed, 12 Aug 2026 17:09:36 +0000 (UTC) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 88C024279E; Wed, 12 Aug 2026 19:08:53 +0200 (CEST) Received: from agw.arknetworks.am (agw.arknetworks.am [79.141.165.80]) by mails.dpdk.org (Postfix) with ESMTP id 690E040E0F; Wed, 12 Aug 2026 19:08:49 +0200 (CEST) Received: from localhost.localdomain (unknown [78.109.70.176]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by agw.arknetworks.am (Postfix) with ESMTPSA id A3C79E0BA6; Wed, 12 Aug 2026 21:08:48 +0400 (+04) DKIM-Filter: OpenDKIM Filter v2.11.0 agw.arknetworks.am A3C79E0BA6 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arknetworks.am; s=default; t=1786554529; bh=UhT1SV9jhgIHnSfgNwNrCJyS+/7A+SpkgQJSYmkvgNo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RdRAf7WeKrjJ//vpr2qMfwINRlLbimwxzXh7GFFXkFiqWAkA0rM6rd6nhZZQUtyS7 rcVvzKpUn81sAz4DSQWsW1QB2VOnAwZH7PJ6aun3iMCBjH6o26iUsp1oXJJ+q3H9wO mCmF6avlpv3oC1my/CknpbUZney+Od9+xO5AhNY8Si9mwGibtwb7LbngDL0rraZJcu sPFosdEpNjkxg632zsAjrBnduz+QZUGqt7E2BN9YXzGzFoH1kDXpfUoWfpzTT2yo1e Y6EP41hQCtDODW++JSwZQPm+53m7qlj3H1OTfmyfZle7vlcc4vzdNaHC0MG473M1uR NZ2CxsF2Wb4vw== From: Ivan Malov To: dev@dpdk.org Cc: Andy Moreton , Viacheslav Galaktionov , Roman Zhukov , Pieter Jansen van Vuuren , Stephen Hemminger , Andrew Rybchenko , stable@dpdk.org Subject: [PATCH v2 07/14] common/sfc_efx/base: fix annotations in HW-SW mask converter Date: Wed, 12 Aug 2026 21:08:27 +0400 Message-ID: <20260812170834.8443-8-ivan.malov@arknetworks.am> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260812170834.8443-1-ivan.malov@arknetworks.am> References: <20260811174821.8930-1-ivan.malov@arknetworks.am> <20260812170834.8443-1-ivan.malov@arknetworks.am> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Andy Moreton Code analysis reports that efx_np_cap_mask_hw_to_sw does not always write to sw_cap_maskp. Fix the annotation to show it is valid on input, and initialise the mask in efx_np_cap_hw_data_to_sw_mask. Fixes: a90549f527eb ("common/sfc_efx/base: get netport fixed capabilities on probe") Cc: stable@dpdk.org Signed-off-by: Andy Moreton Reviewed-by: Ivan Malov Reviewed-by: Viacheslav Galaktionov --- drivers/common/sfc_efx/base/efx_np.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/common/sfc_efx/base/efx_np.c b/drivers/common/sfc_efx/base/efx_np.c index 5044eabdd3..baee83e58e 100644 --- a/drivers/common/sfc_efx/base/efx_np.c +++ b/drivers/common/sfc_efx/base/efx_np.c @@ -190,7 +190,7 @@ efx_np_cap_mask_hw_to_sw( __in unsigned int hw_sw_map_nentries, __in_bcount(hw_cap_data_nbytes) const uint8_t *hw_cap_data, __in size_t hw_cap_data_nbytes, - __out uint32_t *sw_cap_maskp) + __inout uint32_t *sw_cap_maskp) { FOREACH_SUP_CAP(hw_sw_map, hw_sw_map_nentries, hw_cap_data, hw_cap_data_nbytes) { @@ -216,6 +216,8 @@ efx_np_cap_hw_data_to_sw_mask( __in const uint8_t *hw_data, __out uint32_t *sw_maskp) { + *sw_maskp = 0; + EFX_NP_CAP_MASK_HW_TO_SW(efx_np_cap_map_tech, ETH_AN_FIELDS_TECH_MASK, hw_data, sw_maskp); @@ -429,21 +431,21 @@ efx_np_link_state( _NOTE(ARGUNUSED(lbp)) #endif /* EFSYS_OPT_LOOPBACK */ - if (lsp->enls_an_supported != B_FALSE) - lsp->enls_adv_cap_mask |= 1U << EFX_PHY_CAP_AN; - efx_np_cap_hw_data_to_sw_mask( MCDI_OUT2(req, const uint8_t, LINK_STATE_OUT_ADVERTISED_ABILITIES), &lsp->enls_adv_cap_mask); - if (status_flags & (1U << MC_CMD_LINK_STATUS_FLAGS_AN_ABLE)) - lsp->enls_lp_cap_mask |= 1U << EFX_PHY_CAP_AN; + if (lsp->enls_an_supported != B_FALSE) + lsp->enls_adv_cap_mask |= 1U << EFX_PHY_CAP_AN; efx_np_cap_hw_data_to_sw_mask( MCDI_OUT2(req, const uint8_t, LINK_STATE_OUT_LINK_PARTNER_ABILITIES), &lsp->enls_lp_cap_mask); + if (status_flags & (1U << MC_CMD_LINK_STATUS_FLAGS_AN_ABLE)) + lsp->enls_lp_cap_mask |= 1U << EFX_PHY_CAP_AN; + tech = MCDI_OUT_WORD(req, LINK_STATE_OUT_LINK_TECHNOLOGY); if (tech < EFX_ARRAY_SIZE(efx_np_tech_to_lane_count)) -- 2.47.3