From: Bruce Richardson <bruce.richardson@intel.com>
To: dev@dpdk.org
Cc: Bruce Richardson <bruce.richardson@intel.com>,
Vladimir Medvedkin <vladimir.medvedkin@intel.com>
Subject: [PATCH 01/13] net/iavf: remove unnecessary alignment calls
Date: Thu, 3 Sep 2026 18:01:30 +0100 [thread overview]
Message-ID: <20260903170140.360477-2-bruce.richardson@intel.com> (raw)
In-Reply-To: <20260903170140.360477-1-bruce.richardson@intel.com>
When we have a context descriptor on Tx of a packet from the vector
paths, that means that we always have 32-bytes being written per
descriptor/per packet, so the stores are always 32-bit aligned. This
means we can use aligned stores for each single descriptor store, and
that we never need to do an initial descriptor write for alignment when
doing a burst of descriptors.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
drivers/net/intel/iavf/iavf_rxtx_vec_avx2.c | 9 ++-------
drivers/net/intel/iavf/iavf_rxtx_vec_avx512.c | 9 ++-------
2 files changed, 4 insertions(+), 14 deletions(-)
diff --git a/drivers/net/intel/iavf/iavf_rxtx_vec_avx2.c b/drivers/net/intel/iavf/iavf_rxtx_vec_avx2.c
index 7217f32cef..9b62ef53d3 100644
--- a/drivers/net/intel/iavf/iavf_rxtx_vec_avx2.c
+++ b/drivers/net/intel/iavf/iavf_rxtx_vec_avx2.c
@@ -1933,7 +1933,8 @@ ctx_vtx1(volatile struct ci_tx_desc *txdp, struct rte_mbuf *pkt,
__m256i ctx_data_desc = _mm256_set_epi64x(high_data_qw, pkt->buf_iova + pkt->data_off,
high_ctx_qw, low_ctx_qw);
- _mm256_storeu_si256(RTE_CAST_PTR(__m256i *, txdp), ctx_data_desc);
+ /* tx_id is always even in ctx mode, so txdp is always 32-byte aligned */
+ _mm256_store_si256(RTE_CAST_PTR(__m256i *, txdp), ctx_data_desc);
}
static __rte_always_inline void
@@ -1944,12 +1945,6 @@ ctx_vtx(volatile struct ci_tx_desc *txdp,
uint64_t hi_data_qw_tmpl = (IAVF_TX_DESC_DTYPE_DATA |
((uint64_t)flags << IAVF_TXD_QW1_CMD_SHIFT));
- /* if unaligned on 32-bit boundary, do one to align */
- if (((uintptr_t)txdp & 0x1F) != 0 && nb_pkts != 0) {
- ctx_vtx1(txdp, *pkt, flags, offload, vlan_flag, ptype_lldp_enabled);
- nb_pkts--; txdp++; pkt++;
- }
-
for (; nb_pkts > 1; txdp += 4, pkt += 2, nb_pkts -= 2) {
uint64_t hi_ctx_qw1 = IAVF_TX_DESC_DTYPE_CONTEXT;
uint64_t hi_ctx_qw0 = IAVF_TX_DESC_DTYPE_CONTEXT;
diff --git a/drivers/net/intel/iavf/iavf_rxtx_vec_avx512.c b/drivers/net/intel/iavf/iavf_rxtx_vec_avx512.c
index bf0245e8f4..4609c2245a 100644
--- a/drivers/net/intel/iavf/iavf_rxtx_vec_avx512.c
+++ b/drivers/net/intel/iavf/iavf_rxtx_vec_avx512.c
@@ -2078,7 +2078,8 @@ ctx_vtx1(volatile struct ci_tx_desc *txdp, struct rte_mbuf *pkt,
__m256i ctx_data_desc = _mm256_set_epi64x(high_data_qw, pkt->buf_iova + pkt->data_off,
high_ctx_qw, low_ctx_qw);
- _mm256_storeu_si256(RTE_CAST_PTR(__m256i *, txdp), ctx_data_desc);
+ /* tx_id is always even in ctx mode, so txdp is always 32-byte aligned */
+ _mm256_store_si256(RTE_CAST_PTR(__m256i *, txdp), ctx_data_desc);
}
static __rte_always_inline void
@@ -2088,12 +2089,6 @@ ctx_vtx(volatile struct ci_tx_desc *txdp,
{
uint64_t hi_data_qw_tmpl = (CI_TX_DESC_DTYPE_DATA | (flags << CI_TXD_QW1_CMD_S));
- /* if unaligned on 32-bit boundary, do one to align */
- if (((uintptr_t)txdp & 0x1F) != 0 && nb_pkts != 0) {
- ctx_vtx1(txdp, *pkt, flags, offload, vlan_flag, lldp_enabled);
- nb_pkts--; txdp++; pkt++;
- }
-
for (; nb_pkts > 1; txdp += 4, pkt += 2, nb_pkts -= 2) {
uint64_t hi_ctx_qw1 = IAVF_TX_DESC_DTYPE_CONTEXT;
uint64_t hi_ctx_qw0 = IAVF_TX_DESC_DTYPE_CONTEXT;
--
2.53.0
next prev parent reply other threads:[~2026-09-03 17:02 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-03 17:01 [PATCH 00/13] Consolidate ice and iavf vector Tx paths Bruce Richardson
2026-09-03 17:01 ` Bruce Richardson [this message]
2026-09-03 17:01 ` [PATCH 02/13] net/intel: make Tx context flag common Bruce Richardson
2026-09-03 17:01 ` [PATCH 03/13] net/iavf: use separate params for VLAN and QinQ position Bruce Richardson
2026-09-03 17:01 ` [PATCH 04/13] net/iavf: deduplicate tunnel field fill functions Bruce Richardson
2026-09-04 7:01 ` David Marchand
2026-09-03 17:01 ` [PATCH 05/13] net/intel: define common macros for tunneling bit-shifts Bruce Richardson
2026-09-03 17:01 ` [PATCH 06/13] net/intel: move iavf descriptor writing functions to common Bruce Richardson
2026-09-03 17:01 ` [PATCH 07/13] net/intel: use function callback for lldp Bruce Richardson
2026-09-03 17:01 ` [PATCH 08/13] net/ice: use common descriptor creation functions Bruce Richardson
2026-09-03 17:01 ` [PATCH 09/13] net/intel: move vector Tx paths to common Bruce Richardson
2026-09-03 17:03 ` [PATCH 10/13] net/ice: use common AVX Tx functions Bruce Richardson
2026-09-03 17:04 ` [PATCH 11/13] net/intel: add common vector Tx fns with context handling Bruce Richardson
2026-09-03 17:04 ` [PATCH 12/13] net/intel: improve Tx path selection logic Bruce Richardson
2026-09-03 17:04 ` [PATCH 13/13] net/ice: enable context desc offloads for vector Tx Bruce Richardson
2026-09-04 7:10 ` [PATCH 00/13] Consolidate ice and iavf vector Tx paths David Marchand
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