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[204.195.96.226]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-86153a1c1basm1614076b3a.52.2026.09.04.15.10.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Sep 2026 15:10:08 -0700 (PDT) From: Stephen Hemminger To: dev@dpdk.org Cc: Stephen Hemminger , Dariusz Sosnowski , Viacheslav Ovsiienko , Bing Zhao , Ori Kam , Suanming Mou , Matan Azrad Subject: [RFC 2/3] net/mlx5: drop unnecessary STRICT_ALIGN Date: Fri, 4 Sep 2026 15:09:07 -0700 Message-ID: <20260904220953.3105930-3-stephen@networkplumber.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260904220953.3105930-1-stephen@networkplumber.org> References: <20260904220953.3105930-1-stephen@networkplumber.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The transmit inline copy splits the 8 byte case into two 32 bit moves when RTE_ARCH_STRICT_ALIGN is set. Only armv8 aarch32 ever set that flag, and ARMv8 does unaligned access in hardware, so the split gains nothing. Use a single 64 bit move. The destination is inline_data, at offset 4 of a 16 byte aligned dseg, so the 8 byte store is always misaligned. Write it through the unaligned type; a plain uint64_t store there is undefined behaviour and is reported by UBSAN. The debug assertion on the inline data offset goes away with the strict alignment path since the wider move has no such requirement. Signed-off-by: Stephen Hemminger --- drivers/net/mlx5/mlx5_tx.h | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/drivers/net/mlx5/mlx5_tx.h b/drivers/net/mlx5/mlx5_tx.h index 682dc07718..69a18f8a49 100644 --- a/drivers/net/mlx5/mlx5_tx.h +++ b/drivers/net/mlx5/mlx5_tx.h @@ -1437,19 +1437,9 @@ mlx5_tx_dseg_iptr(struct mlx5_txq_data *__rte_restrict txq, dst = (uintptr_t)&dseg->inline_data[0]; src = (uintptr_t)buf; if (len & 0x08) { -#ifdef RTE_ARCH_STRICT_ALIGN - MLX5_ASSERT(dst == RTE_PTR_ALIGN(dst, sizeof(uint32_t))); - *(uint32_t *)dst = *(unaligned_uint32_t *)src; - dst += sizeof(uint32_t); - src += sizeof(uint32_t); - *(uint32_t *)dst = *(unaligned_uint32_t *)src; - dst += sizeof(uint32_t); - src += sizeof(uint32_t); -#else - *(uint64_t *)dst = *(unaligned_uint64_t *)src; + *(unaligned_uint64_t *)dst = *(unaligned_uint64_t *)src; dst += sizeof(uint64_t); src += sizeof(uint64_t); -#endif } if (len & 0x04) { *(uint32_t *)dst = *(unaligned_uint32_t *)src; -- 2.53.0