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[204.195.96.226]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39e3c06423esm4824952a91.15.2026.09.17.09.19.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Sep 2026 09:19:18 -0700 (PDT) Date: Thu, 17 Sep 2026 09:14:43 -0700 From: Stephen Hemminger To: Rahul Bhansali Cc: , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Harman Kalra , Jerin Jacob , Subject: Re: [PATCH 03/14] common/cnxk: fix NIX QINT count reset Message-ID: <20260917091443.0649942e@phoenix.local> In-Reply-To: <20260917071016.2366467-3-rbhansali@marvell.com> References: <20260917071016.2366467-1-rbhansali@marvell.com> <20260917071016.2366467-3-rbhansali@marvell.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Thu, 17 Sep 2026 12:40:05 +0530 Rahul Bhansali wrote: > Fix QINT count reset on NIX queue IRQs register and > unregister. > Queue interrupt will be cleared by individual queue > interrupt operation register update. > > Fixes: f6d567b03d28 ("common/cnxk: support NIX IRQ") > Fixes: 3c100e0e6b9c ("common/cnxk: support per-port RQ in inline device") > Cc: stable@dpdk.org > > Signed-off-by: Rahul Bhansali > --- More detailed AI review: Patch 3/14 common/cnxk: fix NIX QINT count reset ------------------------------------------------ Warning: the inline dev path now clears QINTX_INT with ~0ull (W1C), but roc_nix_register_queue_irqs() still does plt_write64(0, nix->base + NIX_LF_QINTX_INT(q)); before ENA_W1S, and roc_nix_unregister_queue_irqs() does the same. Writing 0 to a W1C register clears nothing, so a stale QINT is still pending when the interrupt is enabled. Use ~0ull in both places. Info: the roc_nix path uses "int64_t val; plt_write64(-val, ...)" while the inl path casts explicitly. Pick one form.