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[144.49.247.98]) by smtp-relay.gmail.com with ESMTPS id 46e09a7af769-80e4271c129sm274683a34.2.2026.09.17.20.24.26 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 Sep 2026 20:24:27 -0700 (PDT) X-Relaying-Domain: broadcom.com X-CFilter-Loop: Reflected Received: by mail-pj1-f69.google.com with SMTP id 98e67ed59e1d1-38ea32e57e2so715861a91.1 for ; Thu, 17 Sep 2026 20:24:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1789701865; x=1790306665; darn=dpdk.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=GAnjTSfbe4Ry7GAcG6PPMT7sAWo5cPIFryyl+9y9bUU=; b=R83NmA0OmN8VU0hSFntbW4Jg/D0SYVg073gRVkwSLAkL3DPFg5AtuPR/2ovJ8EA5EZ zM9u0WjN96u11ybXPwDHo/BnHsKkTqCMSWRxjtk8+Vmjf0QiTnLdssw9op5qvGlboz3I a/6yqMGuHNzQV+I22sAhNInY+SpBA2WHPeNw8= X-Received: by 2002:a17:90b:3d92:b0:398:c315:fa6f with SMTP id 98e67ed59e1d1-39e54b78015mr2808248a91.14.1789701865523; Thu, 17 Sep 2026 20:24:25 -0700 (PDT) X-Received: by 2002:a17:90b:3d92:b0:398:c315:fa6f with SMTP id 98e67ed59e1d1-39e54b78015mr2808199a91.14.1789701864957; Thu, 17 Sep 2026 20:24:24 -0700 (PDT) Received: from nic1-cos.dhcp.broadcom.net ([192.19.220.253]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33c287b023bsm597708eec.23.2026.09.17.20.24.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Sep 2026 20:24:24 -0700 (PDT) From: Mohammad Shuab Siddique X-Google-Original-From: Mohammad Shuab Siddique To: dev@dpdk.org Cc: kishore.padmanabha@broadcom.com, Joseph Wong , stable@dpdk.org, Mohammad Shuab Siddique Subject: [PATCH 2/5] net/bnxt: fix bounds on firmware-reported resource counts Date: Thu, 17 Sep 2026 21:27:23 -0600 Message-ID: <20260918032726.763384-3-Mohammad-Shuab.Siddique@broadcom.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260918032726.763384-1-Mohammad-Shuab.Siddique@broadcom.com> References: <20260918032726.763384-1-Mohammad-Shuab.Siddique@broadcom.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-DetectorID-Processed: b00c1d49-9d2e-4205-b15f-d015386d3d5e X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Joseph Wong When parsing max_ring_grps and max_l2_ctx values from firmware, clamp values if they exceed a 16-bit value. max_hw_ring_grps is received as 32-bit in __bnxt_hwrm_func_qcaps() (the func_qcaps response) but cast to 16-bit when used; add the clamp there and, as defense-in-depth, also in bnxt_hwrm_func_resc_qcaps() in case that response's field ever widens. max_l2_ctx is 16-bit in both responses, but its post-read addition with max_rx_em_flows can overflow a 16-bit sum; widen the addition to 32-bit and clamp the result. Fixes: 2691827e82c ("net/bnxt: add HWRM VNIC alloc") Fixes: 80bf6811fa0 ("net/bnxt: fix L2 context calculation for Thor") Cc: stable@dpdk.org Signed-off-by: Joseph Wong Signed-off-by: Mohammad Shuab Siddique --- drivers/net/bnxt/bnxt.h | 3 +++ drivers/net/bnxt/bnxt_hwrm.c | 16 ++++++++++++---- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index 336de75da0..69455af31f 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -863,6 +863,9 @@ struct bnxt { #define BNXT_P7_MAX_NQ_RING_CNT 512 #define BNXT_P7_CQ_MAX_L2_ENT 8192 +#define BNXT_MAX_RING_GRPS 65535U +#define BNXT_MAX_L2_CTX 65535U + uint32_t flags2; #define BNXT_FLAGS2_PTP_TIMESYNC_ENABLED BIT(0) #define BNXT_FLAGS2_PTP_ALARM_SCHEDULED BIT(1) diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c index aa8152eaa0..765aa7c452 100644 --- a/drivers/net/bnxt/bnxt_hwrm.c +++ b/drivers/net/bnxt/bnxt_hwrm.c @@ -1125,6 +1125,8 @@ static int __bnxt_hwrm_func_qcaps(struct bnxt *bp) HWRM_CHECK_RESULT(); bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps); + if (bp->max_ring_grps > BNXT_MAX_RING_GRPS) + bp->max_ring_grps = BNXT_MAX_RING_GRPS; flags = rte_le_to_cpu_32(resp->flags); flags_ext2 = rte_le_to_cpu_32(resp->flags_ext2); flags_ext3 = rte_le_to_cpu_32(resp->flags_ext3); @@ -1155,8 +1157,10 @@ static int __bnxt_hwrm_func_qcaps(struct bnxt *bp) bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id); bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows); bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs); - if (!BNXT_CHIP_P5_P7(bp) && !bp->pdev->max_vfs) - bp->max_l2_ctx += bp->max_rx_em_flows; + if (!BNXT_CHIP_P5_P7(bp) && !bp->pdev->max_vfs) { + uint32_t l2_ctx = bp->max_l2_ctx + bp->max_rx_em_flows; + bp->max_l2_ctx = (uint16_t)RTE_MIN(l2_ctx, (uint32_t)BNXT_MAX_L2_CTX); + } if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) bp->max_vnics = rte_le_to_cpu_16(BNXT_MAX_VNICS_COS_CLASSIFY); else @@ -1556,12 +1560,16 @@ int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp) bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings); bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings); bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps); + if (bp->max_ring_grps > BNXT_MAX_RING_GRPS) + bp->max_ring_grps = BNXT_MAX_RING_GRPS; /* func_resource_qcaps does not return max_rx_em_flows. * So use the value provided by func_qcaps. */ bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs); - if (!BNXT_CHIP_P5_P7(bp) && !bp->pdev->max_vfs) - bp->max_l2_ctx += bp->max_rx_em_flows; + if (!BNXT_CHIP_P5_P7(bp) && !bp->pdev->max_vfs) { + uint32_t l2_ctx = bp->max_l2_ctx + bp->max_rx_em_flows; + bp->max_l2_ctx = (uint16_t)RTE_MIN(l2_ctx, (uint32_t)BNXT_MAX_L2_CTX); + } if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) bp->max_vnics = rte_le_to_cpu_16(BNXT_MAX_VNICS_COS_CLASSIFY); else -- 2.47.3