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[204.195.112.43]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3a063c1994esm735465a91.17.2026.09.21.08.55.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Sep 2026 08:55:00 -0700 (PDT) Date: Mon, 21 Sep 2026 08:52:05 -0700 From: Stephen Hemminger To: Mohammad Shuab Siddique Cc: dev@dpdk.org, kishore.padmanabha@broadcom.com, Ajit Khaparde Subject: Re: [PATCH] net/bnxt: enable Tx completion coalescing in hardware Message-ID: <20260921085205.5e52f0f9@phoenix.local> In-Reply-To: <20260921025755.1034702-1-Mohammad-Shuab.Siddique@broadcom.com> References: <20260921025755.1034702-1-Mohammad-Shuab.Siddique@broadcom.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Sun, 20 Sep 2026 20:57:55 -0600 Mohammad Shuab Siddique wrote: > From: Mohammad Shuab Siddique > > P7 devices support Tx completion coalescing in hardware: the driver > can program the Tx coalescing parameters during Tx ring allocation > instead of always disabling it. Use the wthresh config option > provided in ethdev to select the coalescing value for the Tx rings. > > A value of 0 disables the feature. A value of 254 for wthresh is the > max allowable setting; the driver converts the provided value to the > nearest power of 2 for the hardware setting (1 rounds up to 2, which > maps to the same COAL_4 setting as an exact 4; 254 rounds up to 256). > > Signed-off-by: Ajit Khaparde > Signed-off-by: Mohammad Shuab Siddique > --- [PATCH] net/bnxt: enable Tx completion coalescing in hardware Error: does not apply to main without fuzz (see summary). Warning: this adds user-visible behaviour keyed off tx_thresh.wthresh. It needs a doc/guides/nics/bnxt.rst entry and a release note.