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[204.195.112.43]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-896c42b06e9sm187909b3a.42.2026.10.08.16.37.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Oct 2026 16:37:32 -0700 (PDT) From: Stephen Hemminger To: dev@dpdk.org Cc: Stephen Hemminger , Anoob Joseph Subject: [PATCH v3 16/29] crypto/octeontx: use IO barrier before doorbell Date: Thu, 8 Oct 2026 16:35:09 -0700 Message-ID: <20261008233649.1260843-17-stephen@networkplumber.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261008233649.1260843-1-stephen@networkplumber.org> References: <20260729175715.165120-1-stephen@networkplumber.org> <20261008233649.1260843-1-stephen@networkplumber.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The doorbell is written with rte_write64_relaxed(), so the barrier before it is what orders the queued instructions against the device. That is device ordering, not SMP ordering: use rte_io_wmb(). Signed-off-by: Stephen Hemminger --- drivers/crypto/octeontx/otx_cryptodev_hw_access.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h index 3104e6d31e..096dcf8f87 100644 --- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h +++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h @@ -203,8 +203,8 @@ static __rte_always_inline void otx_cpt_ring_dbell(struct cpt_instance *instance, uint16_t count) { struct cpt_vf *cptvf = (struct cpt_vf *)instance; - /* Memory barrier to flush pending writes */ - rte_smp_wmb(); + /* Instructions must be visible to the device before the doorbell */ + rte_io_wmb(); otx_cpt_write_vq_doorbell(cptvf, count); } -- 2.53.0