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[204.195.112.43]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-896c42b06e9sm187909b3a.42.2026.10.08.16.37.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Oct 2026 16:37:36 -0700 (PDT) From: Stephen Hemminger To: dev@dpdk.org Cc: Stephen Hemminger , Konstantin Ananyev , Bruce Richardson Subject: [PATCH v3 20/29] eal/x86: move optimized fence out of SMP barrier Date: Thu, 8 Oct 2026 16:35:13 -0700 Message-ID: <20261008233649.1260843-21-stephen@networkplumber.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261008233649.1260843-1-stephen@networkplumber.org> References: <20260729175715.165120-1-stephen@networkplumber.org> <20261008233649.1260843-1-stephen@networkplumber.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org rte_atomic_thread_fence() implemented the seq_cst case by calling the deprecated rte_smp_mb(). Invert the dependency: the lock add based fence moves into rte_atomic_thread_fence(), and rte_smp_mb() goes away with it since the test that was its last user is converted in the preceding patch. The optimization itself must stay; a plain seq_cst fence is an mfence, about twice the cost. No change in generated code. Signed-off-by: Stephen Hemminger Acked-by: Konstantin Ananyev --- lib/eal/x86/include/rte_atomic.h | 37 ++++++++++++++------------------ 1 file changed, 16 insertions(+), 21 deletions(-) diff --git a/lib/eal/x86/include/rte_atomic.h b/lib/eal/x86/include/rte_atomic.h index 20a4baa575..a46bedb0f0 100644 --- a/lib/eal/x86/include/rte_atomic.h +++ b/lib/eal/x86/include/rte_atomic.h @@ -60,23 +60,8 @@ extern "C" { * Basic idea is to use lock prefixed add with some dummy memory location * as the destination. From their experiments 128B(2 cache lines) below * current stack pointer looks like a good candidate. - * So below we use that technique for rte_smp_mb() implementation. */ -static __rte_always_inline void -rte_smp_mb(void) -{ -#ifdef RTE_TOOLCHAIN_MSVC - _mm_mfence(); -#else -#ifdef RTE_ARCH_I686 - asm volatile("lock addl $0, -128(%%esp); " ::: "memory"); -#else - asm volatile("lock addl $0, -128(%%rsp); " ::: "memory"); -#endif -#endif -} - #define rte_io_mb() rte_mb() #define rte_io_wmb() rte_compiler_barrier() @@ -86,17 +71,27 @@ rte_smp_mb(void) /** * Synchronization fence between threads based on the specified memory order. * - * On x86 the __rte_atomic_thread_fence(rte_memory_order_seq_cst) generates full 'mfence' - * which is quite expensive. The optimized implementation of rte_smp_mb is - * used instead. + * On x86 the __rte_atomic_thread_fence(rte_memory_order_seq_cst) generates + * a full 'mfence' which is quite expensive. The optimized lock add on a + * dummy stack location (see above) is used instead. */ static __rte_always_inline void rte_atomic_thread_fence(rte_memory_order memorder) { - if (memorder == rte_memory_order_seq_cst) - rte_smp_mb(); - else + if (memorder != rte_memory_order_seq_cst) { __rte_atomic_thread_fence(memorder); + return; + } + +#ifdef RTE_TOOLCHAIN_MSVC + _mm_mfence(); +#else +#ifdef RTE_ARCH_I686 + asm volatile("lock addl $0, -128(%%esp); " ::: "memory"); +#else + asm volatile("lock addl $0, -128(%%rsp); " ::: "memory"); +#endif +#endif } #ifdef __cplusplus -- 2.53.0