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([192.19.252.250]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-35b19c6c7b4sm16695675eec.24.2026.10.13.03.44.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Oct 2026 03:44:01 -0700 (PDT) From: Tathagat Priyadarshi To: dev@dpdk.org Cc: joshwash@google.com, stephen@networkplumber.org, stable@dpdk.org Subject: [PATCH v2 3/4] net/gve: add cacheline overlap margin to DQO Tx ring Date: Tue, 13 Oct 2026 10:43:47 +0000 Message-ID: <20261013104348.714550-4-tathagat.dpdk@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261013104348.714550-1-tathagat.dpdk@gmail.com> References: <20261012105023.669486-1-tathagat.dpdk@gmail.com> <20261013104348.714550-1-tathagat.dpdk@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Mailman-Approved-At: Tue, 13 Oct 2026 16:49:47 +0200 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The GVNIC DQO hardware DMA engine prefetches descriptors in cacheline units (64 bytes = 4 descriptors of 16 bytes each). When producer tail and consumer head indices share a cacheline, CPU and device DMA memory collisions can occur. Align with the Linux driver (gve_has_tx_slots_available()) by requiring GVE_TX_MIN_DESC_PREVENT_CACHE_OVERLAP (4 descriptors) headroom when checking descriptor availability before enqueueing packets. Fixes: 4022f9999f56 ("net/gve: support basic Tx data path for DQO") Cc: stable@dpdk.org Signed-off-by: Tathagat Priyadarshi Acked-by: Joshua Washington --- drivers/net/gve/gve_tx_dqo.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/net/gve/gve_tx_dqo.c b/drivers/net/gve/gve_tx_dqo.c index 0839179d7f..eee1f10df1 100644 --- a/drivers/net/gve/gve_tx_dqo.c +++ b/drivers/net/gve/gve_tx_dqo.c @@ -260,6 +260,7 @@ gve_tx_burst_dqo(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) uint64_t bytes = 0; const char *reason; uint16_t compl_tag; + uint16_t req_descs; uint64_t ol_flags; uint16_t nb_descs; uint16_t tx_id; @@ -291,14 +292,17 @@ gve_tx_burst_dqo(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) nb_descs = gve_tx_pkt_nb_data_descs(tx_pkt); nb_descs += tso; + req_descs = nb_descs + GVE_TX_MIN_DESC_PREVENT_CACHE_OVERLAP; - /* Clean if there aren't enough descriptors to send the packet. */ - if (unlikely(!gve_can_tx(txq, nb_descs, 1))) { + /* Clean if there aren't enough descriptors to send the packet + * while maintaining the cacheline overlap margin. + */ + if (unlikely(!gve_can_tx(txq, req_descs, 1))) { int nb_to_clean = RTE_MAX(DQO_TX_MULTIPLIER * txq->rs_thresh, - nb_descs); + (int)req_descs); gve_tx_clean_descs_dqo(txq, nb_to_clean); - if (!gve_can_tx(txq, nb_descs, 1)) + if (!gve_can_tx(txq, req_descs, 1)) break; } -- 2.43.0