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[204.195.112.43]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2e8421b19a2sm61865145ad.46.2026.10.13.15.35.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Oct 2026 15:35:05 -0700 (PDT) From: Stephen Hemminger To: dev@dpdk.org Cc: Stephen Hemminger , Konstantin Ananyev , =?UTF-8?q?Morten=20Br=C3=B8rup?= , Wathsala Vithanage Subject: [PATCH v4 12/29] ring: replace SMP read barrier with C11 acquire fence Date: Tue, 13 Oct 2026 15:22:25 -0700 Message-ID: <20261013222410.2257622-13-stephen@networkplumber.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261013222410.2257622-1-stephen@networkplumber.org> References: <20260729175715.165120-1-stephen@networkplumber.org> <20261013222410.2257622-1-stephen@networkplumber.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org rte_smp_rmb() is deprecated. This code is only used where RTE_USE_C11_MEM_MODEL is unset: x86, ppc64, loongarch and ThunderX. The acquire fence generates the same code on x86 (a compiler barrier) and on ThunderX (dmb ishld). On ppc64 the barrier becomes lwsync instead of sync, which still orders load against load. The gcc implementation itself is kept: unlike the lock-free stack, the in-tree comment records a 10% x86 performance drop with the C11 version, which needs re-measuring with current compilers before RTE_USE_C11_MEM_MODEL can be removed. Signed-off-by: Stephen Hemminger Acked-by: Konstantin Ananyev Acked-by: Morten Brørup --- lib/ring/rte_ring_gcc_pvt.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/lib/ring/rte_ring_gcc_pvt.h b/lib/ring/rte_ring_gcc_pvt.h index 340ece28c7..9c2c58824d 100644 --- a/lib/ring/rte_ring_gcc_pvt.h +++ b/lib/ring/rte_ring_gcc_pvt.h @@ -55,10 +55,10 @@ __rte_ring_headtail_move_head_st(struct rte_ring_headtail *d, *old_head = d->head; - /* add rmb barrier to avoid load/load reorder in weak - * memory model. It is noop on x86 + /* Acquire fence to avoid load/load reorder in weak + * memory model. It is noop on x86. */ - rte_smp_rmb(); + rte_atomic_thread_fence(rte_memory_order_acquire); /* * The subtraction is done between two unsigned 32bits value -- 2.53.0