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[204.195.112.43]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2e8421b19a2sm61865145ad.46.2026.10.13.15.35.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Oct 2026 15:35:28 -0700 (PDT) From: Stephen Hemminger To: dev@dpdk.org Cc: Stephen Hemminger , Maxime Coquelin , Chenbo Xia Subject: [PATCH v4 27/29] net/virtio: replace deprecated barrier in avail index update Date: Tue, 13 Oct 2026 15:22:40 -0700 Message-ID: <20261013222410.2257622-28-stephen@networkplumber.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261013222410.2257622-1-stephen@networkplumber.org> References: <20260729175715.165120-1-stephen@networkplumber.org> <20261013222410.2257622-1-stephen@networkplumber.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org As with virtqueue_nused(), the x86 special case only pays off while both arms of the weak_barriers test compile to the same thing, which rules out rte_atomic_thread_fence(rte_memory_order_release). Use rte_io_wmb(), a compiler barrier on x86, where stores are not reordered with other stores. Signed-off-by: Stephen Hemminger --- drivers/net/virtio/virtqueue.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/net/virtio/virtqueue.h b/drivers/net/virtio/virtqueue.h index ee21d43068..8fd2999132 100644 --- a/drivers/net/virtio/virtqueue.h +++ b/drivers/net/virtio/virtqueue.h @@ -474,14 +474,14 @@ static inline void vq_update_avail_idx(struct virtqueue *vq) { if (vq->hw->weak_barriers) { - /* x86 prefers to using rte_smp_wmb over rte_atomic_store_explicit as - * it reports a slightly better perf, which comes from the - * saved branch by the compiler. - * The if and else branches are identical with the smp and - * io barriers both defined as compiler barriers on x86. + /* x86 prefers rte_io_wmb over rte_atomic_store_explicit as it + * reports a slightly better perf, which comes from the saved + * branch by the compiler: on x86 this makes the two branches + * identical, since rte_io_wmb() is only a compiler barrier and + * stores are not reordered with other stores. */ #ifdef RTE_ARCH_X86_64 - rte_smp_wmb(); + rte_io_wmb(); vq->vq_split.ring.avail->idx = vq->vq_avail_idx; #else rte_atomic_store_explicit(&vq->vq_split.ring.avail->idx, -- 2.53.0