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[204.195.112.43]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2e8421b19a2sm61865145ad.46.2026.10.13.15.34.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Oct 2026 15:34:59 -0700 (PDT) From: Stephen Hemminger To: dev@dpdk.org Cc: Stephen Hemminger , Long Li , Wei Hu Subject: [PATCH v4 05/29] bus/vmbus: replace SMP barriers with C11 memory fences Date: Tue, 13 Oct 2026 15:22:18 -0700 Message-ID: <20261013222410.2257622-6-stephen@networkplumber.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261013222410.2257622-1-stephen@networkplumber.org> References: <20260729175715.165120-1-stephen@networkplumber.org> <20261013222410.2257622-1-stephen@networkplumber.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Full barriers order the preceding index store against the following load of the interrupt mask or pending size and stay seq_cst; read barriers become acquire fences. Same code generated on x86 and arm64. The write barrier in rte_vmbus_chan_signal_tx() goes away instead. Every caller reaches it through vmbus_txbr_write(), which ends in vmbus_txbr_need_signal() and its full barrier, so the load of the interrupt mask is already ordered after the write index store. Signed-off-by: Stephen Hemminger Reviewed-by: Long Li Reviewed-by: Wei Hu --- drivers/bus/vmbus/vmbus_bufring.c | 4 ++-- drivers/bus/vmbus/vmbus_channel.c | 13 ++++++------- 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/bus/vmbus/vmbus_bufring.c b/drivers/bus/vmbus/vmbus_bufring.c index 86dc446786..95f03929cb 100644 --- a/drivers/bus/vmbus/vmbus_bufring.c +++ b/drivers/bus/vmbus/vmbus_bufring.c @@ -58,11 +58,11 @@ void vmbus_br_setup(struct vmbus_br *br, void *buf, unsigned int blen) static inline bool vmbus_txbr_need_signal(const struct vmbus_bufring *vbr, uint32_t old_windex) { - rte_smp_mb(); + rte_atomic_thread_fence(rte_memory_order_seq_cst); if (vbr->imask) return false; - rte_smp_rmb(); + rte_atomic_thread_fence(rte_memory_order_acquire); /* * This is the only case we need to signal when the diff --git a/drivers/bus/vmbus/vmbus_channel.c b/drivers/bus/vmbus/vmbus_channel.c index 6887fbad46..90ba3d1ef6 100644 --- a/drivers/bus/vmbus/vmbus_channel.c +++ b/drivers/bus/vmbus/vmbus_channel.c @@ -104,10 +104,9 @@ rte_vmbus_chan_signal_tx(struct rte_vmbus_device *dev, const struct vmbus_channe { const struct vmbus_br *tbr = &chan->txbr; - /* Make sure all updates are done before signaling host */ - rte_smp_wmb(); - - /* If host is ignoring interrupts? */ + /* vmbus_txbr_write() did a full barrier after the write index + * update, no further ordering needed here. + */ if (tbr->vbr->imask) return; @@ -211,7 +210,7 @@ bool rte_vmbus_chan_rx_empty(const struct vmbus_channel *channel) { const struct vmbus_br *br = &channel->rxbr; - rte_smp_rmb(); + rte_atomic_thread_fence(rte_memory_order_acquire); return br->vbr->rindex == br->vbr->windex; } @@ -229,13 +228,13 @@ void rte_vmbus_chan_signal_read(struct rte_vmbus_device *dev, return; /* Make sure reading of pending happens after new read index */ - rte_smp_mb(); + rte_atomic_thread_fence(rte_memory_order_seq_cst); pending_sz = rbr->vbr->pending_send; if (!pending_sz) return; - rte_smp_rmb(); + rte_atomic_thread_fence(rte_memory_order_acquire); write_sz = vmbus_br_availwrite(rbr, rbr->vbr->windex); /* If there was space before then host was not blocked */ -- 2.53.0