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(unknown [10.28.38.254]) by maili.marvell.com (Postfix) with ESMTP id 182F53F704D; Mon, 19 Oct 2026 06:08:16 -0700 (PDT) From: Tejasree Kondoj To: Akhil Goyal CC: Anoob Joseph , Vidya Sagar Velumuri , Ankur Dwivedi , Rupesh Chiluka , Nithin Dabilpuram , Subject: [PATCH 06/16] crypto/cnxk: fix CN20K CPT error recovery Date: Mon, 19 Oct 2026 18:37:47 +0530 Message-ID: <20261019130759.2181566-7-ktejasree@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261019130759.2181566-1-ktejasree@marvell.com> References: <20261019130759.2181566-1-ktejasree@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: e3LeLU__8NHaTKw7AyoawrvnT1HC67cL X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDE5MDA1MiBTYWx0ZWRfX95KC1foNF9p3 8f6jkLu5mAB6vqQp/b+ul9HRf+TPAA5p/XhGWksjfnIpj2LzIt4ResR1rv0KWYtwrb2O5J6td4w pxgdTmmbW8OQqOIh5k21BxKoD2nd+7mrRnsr3Hndr/nZoIf4AQe2ThvNOKxePSmxSQhmLeDVOTn GxkSgvlL0NRmVKogqTi+cPZgk18e+f2q4w3qCkY/z7CgMqupQeGb7Pv6a2E76Zk/D5bTmqt6YpD oPRzKs5Vk/Kt15dKZt2nJk18bCa41BUNLousQfUi4VTN+SnyeMzpY6wvtVEjHO9znCbcVgqReDK FTlUpi1YTd0/L984IaP+t9v9CmA4teK0qIQUamo5GQ3Yz3YoHPoEA/zzA6oDpv1mkXqeZCv7HO8 9eUIpiDzEey3vHjZW6N/QT4Mf7CrytMeEDpEZ3vJpJeZEQo+vlb6r26BjjrJvRl8YfHjwqKesQW r/gBBkA/muhBmxSkD3w== X-Proofpoint-GUID: e3LeLU__8NHaTKw7AyoawrvnT1HC67cL X-Proofpoint-Spam-Info: AW1haW4tMjYxMDE5MDA1MiBTYWx0ZWRfX9HAbs8kBEx1a 6ooG5iyrGGJsWXuiKQkU1JgJllAr4zwuW1dvnRddHwx/hK/sM9a0jV1CaVSVUK7jkdqh5g7PtZ3 ST4enBaIISB9XJpYCgdOO40cVVEW5oM= X-Authority-Analysis: v=2.4 cv=LfupeTfi c=1 sm=1 tr=0 ts=6ad61644 cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=660iZSQnnn4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=QXcCYyLzdtTjyudCfB6f:22 a=M5GUcnROAAAA:8 a=yL3dTDLnE6O-cySBhc8A:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-19_03,2026-10-14_01,2025-10-01_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Reprogram completion queue base and size registers in roc_cpt_cq_enable as hardware clears them after fatal error. Also reset pending queue head and tail during queue pair reset so software completion state stays aligned with the reset hardware queue. Fixes: 13ce9121c3c0 ("common/cnxk: add routines to operate CPT CQ") Fixes: 4e8a41acaffb ("crypto/cnxk: support CPT CQ for CN20K") Signed-off-by: Tejasree Kondoj --- drivers/common/cnxk/roc_cpt.c | 13 +++++++++++++ drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 6 ++++++ 2 files changed, 19 insertions(+) diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c index 8c60a28fff..eae3f134e9 100644 --- a/drivers/common/cnxk/roc_cpt.c +++ b/drivers/common/cnxk/roc_cpt.c @@ -1147,7 +1147,20 @@ roc_cpt_eng_grp_add(struct roc_cpt *roc_cpt, enum cpt_eng_type eng_type) void roc_cpt_cq_enable(struct roc_cpt_lf *lf) { + union cpt_lf_cq_base lf_cq_base = {.u = 0x0}; + union cpt_lf_cq_size lf_cq_size = {.u = 0x0}; union cpt_lf_cq_ctl lf_cq_ctl = {.u = 0x0}; + uintptr_t addr; + + /* Disable completion queue */ + roc_cpt_cq_disable(lf); + + /* Reconfigure CQ base and size, same as cpt_lf_cq_init() */ + addr = (uintptr_t)lf->cq_vaddr; + lf_cq_base.s.addr = addr >> 7; + plt_write64(lf_cq_base.u, lf->rbase + CPT_LF_CQ_BASE); + lf_cq_size.s.size = lf->cq_size; + plt_write64(lf_cq_size.u, lf->rbase + CPT_LF_CQ_SIZE); lf_cq_ctl.s.ena = 1; lf_cq_ctl.s.dq_ack_ena = lf->dq_ack_ena; diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c index 1e0ea9d358..95f64a79ae 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c @@ -596,6 +596,7 @@ cnxk_cpt_queue_pair_reset(struct rte_cryptodev *dev, uint16_t qp_id, { if (conf == NULL) { struct cnxk_cpt_vf *vf = dev->data->dev_private; + struct cnxk_cpt_qp *qp; struct roc_cpt_lf *lf; if (vf == NULL) @@ -603,6 +604,11 @@ cnxk_cpt_queue_pair_reset(struct rte_cryptodev *dev, uint16_t qp_id, lf = vf->cpt.lf[qp_id]; roc_cpt_lf_reset(lf); + + qp = dev->data->queue_pairs[qp_id]; + qp->pend_q.head = 0; + qp->pend_q.tail = 0; + roc_cpt_iq_enable(lf); if (lf->cpt_cq_ena) -- 2.43.0