From: Maayan Kashani <mkashani@nvidia.com>
To: <dev@dpdk.org>
Cc: <mkashani@nvidia.com>, <rasland@nvidia.com>, <stable@dpdk.org>,
Bing Zhao <bingz@nvidia.com>,
Dariusz Sosnowski <dsosnowski@nvidia.com>,
"Viacheslav Ovsiienko" <viacheslavo@nvidia.com>,
Ori Kam <orika@nvidia.com>, Suanming Mou <suanmingm@nvidia.com>,
Matan Azrad <matan@nvidia.com>
Subject: [PATCH] common/mlx5: fix mkey ordering enum
Date: Thu, 22 Oct 2026 10:30:11 +0300 [thread overview]
Message-ID: <20261022073013.72607-1-mkashani@nvidia.com> (raw)
The updated device specification defines relaxed ordering as 0x1 and
reserves 0x2. Update the mkey read-after-write ordering values
accordingly.
Fixes: 5003eaab7e4 ("common/mlx5: update relaxed ordering policy for mkeys")
Cc: stable@dpdk.org
Signed-off-by: Maayan Kashani <mkashani@nvidia.com>
Acked-by: Bing Zhao <bingz@nvidia.com>
---
drivers/common/mlx5/mlx5_prm.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index c2810194f8e..7ae5ece6c32 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -1483,8 +1483,7 @@ enum {
/* MKC read_after_write_ordering field (2-bit, dword 0x38 bits 9:8). */
enum mlx5_mkc_raw_ordering {
MLX5_MKC_RAW_ORDERING_SO = 0x0,
- MLX5_MKC_RAW_ORDERING_SAO = 0x1,
- MLX5_MKC_RAW_ORDERING_RO = 0x2,
+ MLX5_MKC_RAW_ORDERING_RO = 0x1,
};
struct mlx5_ifc_create_mkey_out_bits {
--
2.21.0
next reply other threads:[~2026-10-22 7:30 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-22 7:30 Maayan Kashani [this message]
2026-10-22 9:47 ` [PATCH v2] common/mlx5: fix mkey ordering enum Maayan Kashani
2026-10-26 12:54 ` [PATCH v3] " Maayan Kashani
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