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Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH01EPF000BE949.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8779 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Archive: List-Post: List-Help: List-Subscribe: , X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 The updated device specification defines relaxed ordering as 0x1 and reserves 0x2. Update the mkey read-after-write ordering values accordingly. Fixes: 5003eaab7e49 ("common/mlx5: update relaxed ordering policy for mkeys") Cc: stable@dpdk.org Signed-off-by: Maayan Kashani Acked-by: Bing Zhao --- drivers/common/mlx5/mlx5_prm.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index c2810194f8e..7ae5ece6c32 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -1483,8 +1483,7 @@ enum { /* MKC read_after_write_ordering field (2-bit, dword 0x38 bits 9:8). */ enum mlx5_mkc_raw_ordering { MLX5_MKC_RAW_ORDERING_SO = 0x0, - MLX5_MKC_RAW_ORDERING_SAO = 0x1, - MLX5_MKC_RAW_ORDERING_RO = 0x2, + MLX5_MKC_RAW_ORDERING_RO = 0x1, }; struct mlx5_ifc_create_mkey_out_bits { -- 2.21.0