From: Bing Zhao <bingz@nvidia.com>
To: Dariusz Sosnowski <dsosnowski@nvidia.com>,
Viacheslav Ovsiienko <viacheslavo@nvidia.com>,
Bing Zhao <bingz@nvidia.com>, Ori Kam <orika@nvidia.com>,
Suanming Mou <suanmingm@nvidia.com>,
Matan Azrad <matan@nvidia.com>
Cc: <dev@dpdk.org>, Erez Shitrit <erezsh@nvidia.com>, <stable@dpdk.org>
Subject: [PATCH] net/mlx5/hws: add the DF bit for IPv4 header in NAT64 action
Date: Wed, 28 Oct 2026 03:50:17 +0000 [thread overview]
Message-ID: <20261028035017.3900338-1-bingz@nvidia.com> (raw)
From: Erez Shitrit <erezsh@nvidia.com>
We set the DF bit to 1, and re-calculate the csum for that buffer.
Fixes: 06d969a8c5b8 ("net/mlx5/hws: support NAT64 flow action")
Cc: stable@dpdk.org
Signed-off-by: Erez Shitrit <erezsh@nvidia.com>
Acked-by: Bing Zhao <bingz@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
drivers/net/mlx5/hws/mlx5dr_action.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/net/mlx5/hws/mlx5dr_action.c b/drivers/net/mlx5/hws/mlx5dr_action.c
index 498c6aa109..3e48739eb5 100644
--- a/drivers/net/mlx5/hws/mlx5dr_action.c
+++ b/drivers/net/mlx5/hws/mlx5dr_action.c
@@ -507,8 +507,11 @@ mlx5dr_action_create_nat64_repalce_state(struct mlx5dr_context *ctx,
memcpy(address_prefix, nat64_well_known_pref,
MLX5DR_ACTION_NAT64_HEADER_MINUS_ONE * sizeof(uint32_t));
} else {
- /* In order to fix HW csum issue, make the prefix ready */
- uint32_t ipv4_pref[] = {0x0, 0xffba0000, 0x0, 0x0, 0x0};
+ /* We make a buffer that contain the right HW csum and the DF bit set.
+ * 0x00400000 - contain the DF bit in the right place.
+ * 0xff7a0000 - is the csum for that buffer, calculated via external tool.
+ */
+ uint32_t ipv4_pref[] = {0x00400000, 0xff7a0000, 0x0, 0x0, 0x0};
header_size_in_dw = MLX5DR_ACTION_NAT64_IPV4_HEADER;
ip_ver = MLX5DR_ACTION_NAT64_IPV4_VER;
--
2.34.1
reply other threads:[~2026-10-28 3:51 UTC|newest]
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