From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thomas Monjalon Subject: Re: [dpdk-stable] [PATCH] eal/ppc: remove fix of memory barrier for IBM POWER Date: Thu, 28 Mar 2019 23:50:28 +0100 Message-ID: <2107406.dfrop5AP8K@xps> References: <1552913893-43407-1-git-send-email-dekelp@mellanox.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7Bit Cc: stable@dpdk.org, chaozhu@linux.vnet.ibm.com, yskoh@mellanox.com, shahafs@mellanox.com, dev@dpdk.org, orika@mellanox.com, pradeep@us.ibm.com, David Christensen To: Dekel Peled Return-path: In-Reply-To: <1552913893-43407-1-git-send-email-dekelp@mellanox.com> List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" 18/03/2019 13:58, Dekel Peled: > From previous patch description: "to improve performance on PPC64, > use light weight sync instruction instead of sync instruction." > > Excerpt from IBM doc [1], section "Memory barrier instructions": > "The second form of the sync instruction is light-weight sync, > or lwsync. > This form is used to control ordering for storage accesses to system > memory only. It does not create a memory barrier for accesses to > device memory." > > This patch removes the use of lwsync, so calls to rte_wmb() and > rte_rmb() will provide correct memory barrier to ensure order of > accesses to system memory and device memory. > > [1] https://www.ibm.com/developerworks/systems/articles/powerpc.html > > Fixes: d23a6bd04d72 ("eal/ppc: fix memory barrier for IBM POWER") > Cc: stable@dpdk.org > > Signed-off-by: Dekel Peled Applied, thanks