From: Thomas Monjalon <thomas@monjalon.net>
To: Bing Zhao <bingz@nvidia.com>
Cc: dev@dpdk.org, stable@dpdk.org, wathsala.vithanage@arm.com,
bruce.richardson@intel.com, honnappa.nagarahalli@arm.com,
ruifeng.wang@arm.com
Subject: Re: [PATCH] config/arm: fix the cacheline size for Grace CPU
Date: Tue, 17 Mar 2026 10:55:42 +0100 [thread overview]
Message-ID: <2191545.bB369e8A3T@thomas> (raw)
In-Reply-To: <20260317091732.289777-1-bingz@nvidia.com>
17/03/2026 10:17, Bing Zhao:
> The Nvidia Grace platform has a cacheline size with 64B, unlike the
> 128B size on other arm64 generic platforms. In the meson file, the
> cacheline size is missing to be defined explicitly. So it will choose
> 128 for building and it will impact the performance.
Grace has
'implementer': '0x41',
which is implementer_arm with
['RTE_CACHE_LINE_SIZE', 64],
so I think this patch is not required.
> @@ -535,6 +535,9 @@ soc_grace = {
> 'implementer': '0x41',
> 'part_number': '0xd4f',
> 'extra_march_features': ['crypto'],
> + 'flags': [
> + ['RTE_CACHE_LINE_SIZE', '"64"'],
> + ],
prev parent reply other threads:[~2026-03-17 9:55 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-17 9:17 [PATCH] config/arm: fix the cacheline size for Grace CPU Bing Zhao
2026-03-17 9:55 ` Thomas Monjalon [this message]
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