From mboxrd@z Thu Jan  1 00:00:00 1970
From: Thomas Monjalon <thomas.monjalon@6wind.com>
Subject: Re: [PATCH v2 0/3] add support for HTM lock elision for
	x86
Date: Wed, 17 Jun 2015 15:14:49 +0200
Message-ID: <2512427.xQU6O25ACN@xps13>
References: <1433250693-23644-1-git-send-email-roman.dementiev@intel.com>
 <1434475006-13732-1-git-send-email-roman.dementiev@intel.com>
 <20150617130551.GA8208@bricha3-MOBL3>
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To: Bruce Richardson <bruce.richardson@intel.com>
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2015-06-17 14:05, Bruce Richardson:
> On Tue, Jun 16, 2015 at 10:16:43AM -0700, Roman Dementiev wrote:
> > This series of patches adds methods that use hardware memory transactions (HTM)
> > on fast-path for DPDK locks (a.k.a. lock elision). Here the methods are
> > implemented for x86 using Restricted Transactional Memory instructions (Intel(r)
> > Transactional Synchronization Extensions). The implementation fall-backs to
> > the normal DPDK lock if HTM is not available or memory transactions fail. This
> > is not a replacement for ALL lock usages since not all critical sections
> > protected by locks are friendly to HTM. For example, an attempt to perform
> > a HW I/O operation inside a hardware memory transaction always aborts
> > the transaction since the CPU is not able to roll-back should the transaction
> > fail. Therefore, hardware transactional locks are not advised to be used around
> > rte_eth_rx_burst() and rte_eth_tx_burst() calls.
> > 
> > v2 changes
> > -added a documentation note about hardware limitations
> > 
> > Roman Dementiev (3):
> >   spinlock: add support for HTM lock elision for x86
> >   rwlock: add support for HTM lock elision for x86
> >   test scaling of HTM lock elision protecting rte_hash
> > 
> A change with a conflict in the test makefile was merged last night. However,
> the patches themselves otherwise seem ok. 

Does it mean you ack these patches and they can be blindly applied
without double checking?

> Thomas, is a V3 needed for this small conflict, or can you handle it on applying
> the patch?

Don't worry about conflicts.