From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thomas Monjalon Subject: Re: [PATCH] EAL:fix memory barrier implementation on IBM POWER Date: Thu, 21 Jul 2016 16:24:23 +0200 Message-ID: <2952292.tI9mo3Bcbg@xps13> References: <1468549819-22764-1-git-send-email-chaozhu@linux.vnet.ibm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7Bit Cc: dev@dpdk.org To: Chao Zhu Return-path: Received: from mail-lf0-f46.google.com (mail-lf0-f46.google.com [209.85.215.46]) by dpdk.org (Postfix) with ESMTP id 487C54CE6 for ; Thu, 21 Jul 2016 16:24:25 +0200 (CEST) Received: by mail-lf0-f46.google.com with SMTP id b199so63570466lfe.0 for ; Thu, 21 Jul 2016 07:24:25 -0700 (PDT) In-Reply-To: <1468549819-22764-1-git-send-email-chaozhu@linux.vnet.ibm.com> List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" 2016-07-15 10:30, Chao Zhu: > On weak memory order architecture like POWER, rte_smp_wmb/rte_smp_rmb > need to use CPU instructions, not compiler barrier. This patch fixes > this. Also, to improve performance on PPC64, use light weight sync > instruction instead of sync instruction. > > Signed-off-by: Chao Zhu Applied, thanks