From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Coquelin Subject: Re: [PATCH] bus/pci: forbid VA as IOVA mode if IOMMU address width too small Date: Mon, 8 Jan 2018 17:48:46 +0100 Message-ID: <2ee389ac-1915-d9dd-01aa-0447b4f0008f@redhat.com> References: <20180108135127.25869-1-maxime.coquelin@redhat.com> <20180108073841.43c15072@xeon-e3> <62b32cc7-68a8-806c-d4fb-e15addbeabfb@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Cc: dev@dpdk.org, stable@dpdk.org, jianfeng.tan@intel.com, santosh.shukla@caviumnetworks.com, anatoly.burakov@intel.com, thomas@monjalon.net, peterx@redhat.com To: Stephen Hemminger Return-path: In-Reply-To: <62b32cc7-68a8-806c-d4fb-e15addbeabfb@redhat.com> Content-Language: en-US List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 01/08/2018 04:54 PM, Maxime Coquelin wrote: > > > On 01/08/2018 04:38 PM, Stephen Hemminger wrote: >> On Mon,  8 Jan 2018 14:51:27 +0100 >> Maxime Coquelin wrote: >> >>> +static inline bool >>> +pci_one_device_iommu_support_va(struct rte_pci_device *dev) >>> +{ >>> +#if defined(RTE_ARCH_PPC_64) >>> +    return false; >>> +#elif defined(RTE_ARCH_X86) >>> + >> >> The cleaner way to handle this kind of ifdef is: >> >> #ifdef RTE_ARCH_X86 >> static bool >> pci_one_device_iommu_support_va(struct rte_pci_device *dev) >> { >> .... >> } >> #elif defined(RTE_ARCH_PPC_64) >> static inline bool >> pci_one_device_iommu_support_va(struct rte_pci_device *dev) >> { >>     return false; >> } >> #endif > > Ok, thanks. I do this in v2. > >> What about AMD64? > > I haven't checked AMD64 spec yet. From AMD IOMMU spec (see [0], page 178), the only supported Guest Virtual Address size is 48bits, so above the 47 bits of user VA on x86. So in this regard, AMD IOMMU is compatible with using VA as IOVA. Cheers, Maxime [0]: https://support.amd.com/TechDocs/48882_IOMMU.pdf