From mboxrd@z Thu Jan  1 00:00:00 1970
From: Thomas Monjalon <thomas.monjalon@6wind.com>
Subject: Re: [PATCH v4 1/2] eal/tile: add rte_vect.h and enable
	CONFIG_RTE_LIBRTE_LPM
Date: Thu, 17 Mar 2016 15:04:37 +0100
Message-ID: <3032329.TjjI67JjVh@xps13>
References: <1452263948-22485-1-git-send-email-lsun@ezchip.com>
 <1455077070-6666-1-git-send-email-lsun@ezchip.com> <1561679.Mbe3omy2mz@xps13>
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Cc: dev@dpdk.org, Zhigang Lu <zlu@ezchip.com>
To: Liming Sun <lsun@ezchip.com>
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Any news? a v5 could be part of the RC2.

2016-03-08 20:59, Thomas Monjalon:
> 2016-02-09 23:04, Liming Sun:
> > rte_vect.h was missing earlier thus LPM was disabled and l3fwd is
> > not able to compile. This commit implements the vector api and
> > enable LPM in the tilegx configuration by default.
> > 
> > Signed-off-by: Liming Sun <lsun@ezchip.com>
> > Acked-by: Zhigang Lu <zlu@ezchip.com>
> [...]
> >  # This following libraries are not available on the tile architecture.
> >  # So they're turned off.
> > -CONFIG_RTE_LIBRTE_LPM=n
> > +CONFIG_RTE_LIBRTE_LPM=y
> 
> You just have to remove the disabling line.
> 
> > +typedef union rte_xmm {
> > +	__m128i x;
> > +	uint32_t u32[XMM_SIZE / sizeof(uint32_t)];
> > +	uint64_t u64[XMM_SIZE / sizeof(uint64_t)];
> > +} rte_xmm_t;
> 
> Why do you mimic SSE?
> 
> > +/* Shifts right the 4 32-bit integers by count bits with zeros. */
> > +#define _mm_srli_epi32(v, cnt) ({                  \
> > +	rte_xmm_t m;                                 \
> > +	m.u64[0] = __insn_v4shru(((rte_xmm_t*)&(v))->u64[0], cnt); \
> > +	m.u64[1] = __insn_v4shru(((rte_xmm_t*)&(v))->u64[1], cnt); \
> > +	(m.x);                                       \
> > +})
> 
> Please check the work in progress to have arch-specific implementation
> of rte_lpm_lookupx4():
> 	http://dpdk.org/dev/patchwork/patch/10478/