From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thomas Monjalon Subject: Re: [PATCH v5 00/29] introduce I/O device memory read/write operations Date: Wed, 18 Jan 2017 17:25:22 +0100 Message-ID: <3075116.xAOueQvdyS@xps13> References: <1484637244-7548-1-git-send-email-jerin.jacob@caviumnetworks.com> <1484702502-25451-1-git-send-email-jerin.jacob@caviumnetworks.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7Bit Cc: dev@dpdk.org, konstantin.ananyev@intel.com, bruce.richardson@intel.com, jianbo.liu@linaro.org, viktorin@rehivetech.com, santosh.shukla@caviumnetworks.com To: Jerin Jacob Return-path: Received: from mail-lf0-f53.google.com (mail-lf0-f53.google.com [209.85.215.53]) by dpdk.org (Postfix) with ESMTP id 573BAFAB9 for ; Wed, 18 Jan 2017 17:25:25 +0100 (CET) Received: by mail-lf0-f53.google.com with SMTP id n124so16141988lfd.2 for ; Wed, 18 Jan 2017 08:25:25 -0800 (PST) In-Reply-To: <1484702502-25451-1-git-send-email-jerin.jacob@caviumnetworks.com> List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" 2017-01-18 06:51, Jerin Jacob: > Based on the discussion in the below-mentioned thread, > http://dev.dpdk.narkive.com/DpIRqDuy/dpdk-dev-patch-v2-i40e-fix-eth-i40e-dev-init-sequence-on-thunderx > > This patchset introduces 8-bit, 16-bit, 32bit, 64bit I/O device > memory read/write operations along with the relaxed versions. > > The weakly-ordered machine like ARM needs additional I/O barrier for > device memory read/write access over PCI bus. > By introducing the EAL abstraction for I/O device memory read/write access, > The drivers can access I/O device memory in architecture-agnostic manner. > > The relaxed version does not have additional I/O memory barrier, useful in > accessing the device registers of integrated controllers which > implicitly strongly ordered with respect to memory access. Applied, thanks Does it deserve an entry in the release notes?