From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thomas Monjalon Subject: Re: [PATCH] eal: fix max number of interrupt request Date: Fri, 10 Feb 2017 11:18:43 +0100 Message-ID: <3158466.ioj3dkTVO6@xps13> References: <1486670383-5286-1-git-send-email-qi.z.zhang@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7Bit Cc: dev@dpdk.org, jingjing.wu@intel.com To: Qi Zhang Return-path: Received: from mail-wr0-f172.google.com (mail-wr0-f172.google.com [209.85.128.172]) by dpdk.org (Postfix) with ESMTP id A0CF3952 for ; Fri, 10 Feb 2017 11:18:44 +0100 (CET) Received: by mail-wr0-f172.google.com with SMTP id 89so104232195wrr.2 for ; Fri, 10 Feb 2017 02:18:44 -0800 (PST) In-Reply-To: <1486670383-5286-1-git-send-email-qi.z.zhang@intel.com> List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" 2017-02-09 14:59, Qi Zhang: > The max number of interrupt request is possible > be changed after rte_intr_callback_register, so > in get_max_intr, we need to check if nessesary to > update the max_intr. So you are using rte_intr_enable() to update the max_intr field in the case of VFIO_MSIX. What about MSI, INTX and UIO cases?